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(00,&52(/(&7521,&0$5,16$ ? em microelectronic-marin sa, 9/99, rev. b/275 1 em6521 4 bit microcontroller features low power - 11 a active mode, lcd on - 1.8 a standby mode, lcd off - 0.1 a sleep mode @ 3 v, 32 khz, 25 oc large voltage range, 2 to 5.5 v 2 clocks per instruction cycle 72 basic instructions eeprom 4096 x 16 bits ram 128 x 4 bits max. 12 inputs ; port a, port b, port sp max. 8 outputs ; port b, port sp voltage level detector, 8 levels software selectable from 1.2 v up to 4.0 v melody, 7 tones + silence inclusive 4-bit timer universal 10-bit counter, pwm, event counter prescaler down to 1 second ( crystal = 32 khz ) 1/1000 sec 12 bit binary coded decimal counter with hard or software start/stop function lcd 20 segments, 3 or 4 times multiplexed 3 wire serial port , 8 bit, master and slave mode 5 external interrupts (port a, serial interface) 8 internal interrupts (3x prescaler, bcd counter 2x10-bit counter, melody timer, serial interface) timer watchdog and oscillation supervisor description the em6521is an advanced single chip cmos 4-bit microcontroller. it contains eeprom, ram, lcd driver, power on reset, watchdog timer, oscillation detection circuit, 10-bit up/down and event counter, 1ms bcd counter, prescaler, voltage level detector (vld), serial interface and several clock functions. the low voltage feature and low power consumption make it the most suitable controller for battery, stand alone and mobile equipment. the em6521 is manufactured using em marin's advanced low power (alp) cmos process. typical applications timing device automotive controls with display intelligent display driver measurement equipment domestic appliance interactive system with display timer / sports timing devices bicycle computers safety and security devices figure 1. architecture figure 2. pin configuration, tqfp52 10 * 10 * 1 mm
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 2 em6521 at a glance ? power supply - low voltage low power architecture including internal voltage regulator - 2.0 5.5 v battery voltage - 11 a in active mode (xtal, lcd on, 25 c) - 1.8 a in standby mode (xtal, lcd off, 25 c) - 0.1 a in sleep mode (25 c) - 32 khz oscillator ? ram - 64 x 4 bit, direct addressable - 64 x 4 bit, indexed addressable ? eeprom - 4096 x 16 bit, metal mask programmable ? cpu - 4-bit risc architecture - 2 clock cycles per instruction - 72 basic instructions ? main operating modes and resets - active mode (cpu is running) - standby mode (cpu in halt) - sleep mode (no clock, reset state) - watchdog reset (logic and oscillation watchdogs) - reset terminal and por - reset with input combination on port a (register selectable) ? liquid crystal display driver (lcd) - 20 segments 3 or 4 times multiplexed - internal or external voltage multiplier - free segment allocation architecture - lcd switch off for power save ? 8-bit serial interface - 3 wire master/slave mode - ready output during data transfer - maximum shift clock is equal to system clock - interrupt request to the cpu after 8 bits - supports different serial formats - can be configured as a parallel 4 bit i/o port - direct input read on the port terminals - all outputs can be put tristate (default) - selectable pull resistors in input mode - cmos or nch. open drain outputs ? millisecond counter - 3 digits binary coded decimal counter (12 bits) - pa[3] input pulse width and period measurement - internal 1000 hz clock generation - hardware or software controlled start stop mode - interrupt request on either 1/10 sec or 1sec ? 4-bit input port a - direct input read on the port terminals - debouncer function available on all inputs - interrupt request on positive or negative edge - pull resistor selectable by register - test variables (software) for conditional jumps - pa[0] and pa[3] are inputs for the event counter - pa[3] is start/stop input for the millisecond counter - reset with input combination ? 4-bit bi-directional port b - all different functions bit-wise selectable - direct input read on the port terminals - data output latches - cmos or nch. open drain outputs - pull-down or pull-up selectable - selectable pwm, 32khz, 1khz and 1hz output ? prescaler - 15 stage system clock divider down to 1hz - 3 interrupt requests; 1hz, 32hz or 8hz, blink - prescaler reset (4khz to 1hz) ? voltage level detector (svld) - 8 different levels from 1.2 v to 4.0 v (rom version) - busy flag during measure ? 10-bit universal counter - 10, 8, 6 or 4 bit up/down counting - parallel load - event counting (pa[0] or pa[3]) - 8 different input clocks - full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - hi-frequency input on pa[3] and pa[0] - pulse width modulation ( pwm ) output ? melody generator - dedicated buzzer terminal - 7 tones plus silence output - the output can be put tristate (default) - internal 4-bit timer, usable also in standalone mode - 4 different timer input clocks - timer with automatic reload or single run - timer interrupt request when reaching 0 ? interrupt controller - 5 external and 8 internal interrupt request sources - each interrupt request can individually be masked - each interrupt flag can individually be reset - automatic reset of each interrupt request after read - general interrupt request to cpu can be disabled - automatic enabling of general interrupt request flag when going into halt mode
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 3 table of contents features 1 description 1 typical applications 1 em6521 at a glance 2 1 pin description for em6521 4 1.1 programming connections 6 2 operating modes 7 2.1 active mode 7 2.2 standby mode 7 2.3 sleep mode 7 3 power supply 8 4 reset 9 4.1 oscillation detection circuit 10 4.2 reset terminal 10 4.3 input port a reset function 10 4.4 digital watchdog timer reset 11 4.5 cpu state after reset 11 5 oscillator and prescaler 12 5.1 oscillator 12 5.2 prescaler 12 6 input and output ports 14 6.1 ports overview 14 6.2 port a 15 6.2.1 irq on port a 15 6.2.2 pull-up or pull-down 16 6.2.3 software test variables 16 6.2.4 port a for 10-bit counter and msc 16 6.3 port a registers 16 6.4 port b 18 6.4.1 input / output mode 18 6.4.2 pull-up or pull-down 19 6.4.3 cmos / nch. open drain output 19 6.4.4 pwm and frequency output 20 6.5 port b registers 20 6.6 port serial 21 6.6.1 4-bit parallel i/o 21 6.6.2 pull-up or pull-down 22 6.6.3 nch. open drain outputs 23 6.6.4 general functional description 23 6.6.5 detailed functional description 24 6.6.6 output modes 24 6.6.7 reset and sleep on port sp 25 6.7 serial interface registers 26 7 melody, buzzer 28 7.1 4-bit timer 28 7.1.1 single run mode 29 7.1.2 continuos run mode 29 7.2 programming order 30 7.3 melody registers 30 8 10-bit counter 32 8.1 full and limited bit counting 32 8.2 frequency select and up/down counting 33 8.3 event counting 34 8.4 compare function 34 8.5 pulse width modulation (pwm) 34 8.5.1 how the pwm generator works. 35 8.5.2 pwm characteristics 35 8.6 counter setup 36 8.7 10-bit counter registers 36 9 millisecond counter 38 9.1 pa[3] input for msc 38 9.2 irq from msc 38 9.3 msc-modes 39 9.4 mode selection 39 9.5 millisecond counter registers 41 10 interrupt controller 42 10.1 interrupt control registers 43 11 supply voltage level detector 44 11.1 svld register 44 12 strobe output 45 12.1 strobe register 45 13 ram 46 14 lcd driver 47 14.1 lcd control 48 14.2 lcd addressing 48 14.3 free segment allocation 49 14.4 lcd registers 49 15 peripheral memory map 51 16 option register memory map 55 17 active supply current test 56 18 mask options 57 18.1 input / output ports 57 18.1.1 port a metal options 57 18.1.2 port b metal options 58 18.1.3 port sp metal options 59 18.1.4 voltage regulator option 59 18.1.5 debouncer frequency option 60 18.1.6 user defined lcd segment allocation 60 19 measured electrical behaviors 61 19.1 idd current 61 19.2 regulator voltage 61 19.3 pull resistors 61 19.4 output currents 62 20 em6521 electrical specification 63 20.1 absolute maximum ratings 63 20.2 handling procedures 63 20.3 standard operating conditions 63 20.4 dc characteristics - power supply 63 20.5 supply voltage level detector 64 20.6 oscillator 64 20.7 dc characteristics - i/o pins 65 20.8 lcd seg[20:1] outputs 66 20.9 lcd com[4:1] outputs 66 20.10 dc output component 66 20.11 lcd voltage multiplier 66 21 die, pad location and size 67 22 tqf52 package dimensions 68 23 ordering information 69 23.1 packaged devices 69 23.2 die form 69
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 4 1 pin description for em6521 chip tqfp 52 dil 64 signal name function remarks 1 1 10 vl1 voltage multiplier level 1 lcd level 1 input, if external supply selected 2 2 11 vl2 voltage multiplier level 2 lcd level 2 input, if external supply selected 3 3 12 vl3 voltage multiplier level 3 lcd level 3 input, if external supply selected 4 4 13 com[1] lcd back plane 1 5 5 14 com[2] lcd back plane 2 6 6 15 com[3] lcd back plane 3 7 7 16 com[4] lcd back plane 4 not used if 3 times multiplexed 8 8 18 seg[20] lcd segment 20 9 9 19 seg[19] lcd segment 19 10 10 20 seg[18] lcd segment 18 11 11 21 seg[17] lcd segment 17 12 12 22 seg[16] lcd segment 16 13 13 23 seg[15] lcd segment 15 14 14 26 seg[14] lcd segment 14 15 15 27 seg[13] lcd segment 13 16 16 28 seg[12] lcd segment 12 17 17 29 seg[11] lcd segment 11 18 18 30 seg[10] lcd segment 10 19 19 31 seg[9] lcd segment 9 20 20 33 seg[8] lcd segment 8 21 21 34 seg[7] lcd segment 7 22 22 35 seg[6] lcd segment 6 23 23 36 seg[5] lcd segment 5 24 24 37 seg[4] lcd segment 4 25 25 38 seg[3] lcd segment 3 26 26 39 seg[2] lcd segment 2 27 27 42 seg[1] lcd segment 1 28 28 43 reset input reset terminal, internal pull-down 15 kohm main reset 29 29 44 test input test terminal, internal pull-down 15 kohm for em tests only, ground 0 ! except when needed for mfp programming 30 30 45 psp[0] input/output , open drain serial port : sin parallel out terminal 0 serial interface data in or parallel data[0] in/out 31 31 46 psp[1] output , open drain serial port : ready/cs parallel out terminal 1 serial interface ready cs or parallel data[1] in/out 32 32 47 psp[2] output , open drain serial port : sout parallel out terminal 2 serial interface data out or parallel data[2] in/out 33 33 49 psp[3] input/output , open drain serial port : sclk parallel out terminal 3 serial interface clock i/o or parallel data[3] in/out 34 34 50 pb[0] input/output, open drain port b terminal 0 port b data[0] i/o or ck[1] output
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 5 chip tqfp 52 dil 64 signal name function remarks 35 35 51 pb[1] input/output, open drain port b terminal 1 port b data[1] i/o or ck[11] output 36 36 52 pb[2] input/output, open drain port b terminal 2 port b data[2] i/o or ck[16] output 37 37 53 pb[3] input/output, open drain port b terminal 3 port b data[3] i/o or pwm output 38 38 54 pa[0] input port a terminal 0 testvar 1 event counter 39 39 55 pa[1] input port a terminal 1 testvar 2 40 40 58 pa[2] input port a terminal 2 testvar 3 41 41 59 pa[3] input port a terminal 3 event counter, msc start/stop control 42 42 60 buzzer output buzzer terminal 43 43 61 strobe output strobe terminal p reset state or/and port b write or sleep flag out 44 44 62 vbat = v dd positive power supply mfp connection 45 45 63 vreg internal voltage regulator connect to minimum 100nf, mfp connection 46 46 64 qin/osc1 crystal terminal 1 32 khz crystal, mfp connection 47 47 2 qout /osc2 crystal terminal 2 32 khz crystal, mfp connection 48 48 3 v ss negative power supply ref. terminal, mfp connection 49 49 4 c2b voltage multiplier not needed if ext. supply 50 50 5 c2a voltage multiplier not needed if ext. supply 51 51 6 c1b voltage multiplier not needed if ext. supply 52 52 7 c1a voltage multiplier not needed if ext. supply gray shaded areas : terminals needed for mfp programming connections (v dd , vreg, qin, qout, test). see also programming connections. em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 6 figure 3. typical configuration crystal lcd display c1 c1 c1 c4 c3 vreg v ss test reset v dd (vbat) seg[20:1] q in o out c2 c2 c1a c1b c2a c2b com[4:1] vl1 vl2 vl3 em6521 all capacitors 100nf port a strobe buzzer port b port sp 1.1 programming connections the em6521 can be programmed using the standard em mfp programming box for 4 bit ucontrollers. the interface signals are listed in the table below. the circuit can be programmed on the programming box or directly on the pcb . for more information please refer to the mfp programmers manual. chip tqfp 52 dil 64 signal name function remarks 29 29 44 test input test terminal internal pull-down 15k usually 1 in mfp mode, 0 resets the mfp interface 44 44 62 vbat = v dd positive power supply mfp power connection 45 45 63 vreg internal voltage regulator mfp power connection, adapts the oscillator voltage to vbat 46 46 64 qin/osc1 crystal terminal mfp serial data input / output 47 47 2 qout /osc2 crystal terminal mfp serial clock input 48 48 3 v ss negative power supply mfp connection, reference terminal
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 7 2 operating modes the em6521 has two low power dissipation modes, standby and sleep. figure 4 is a transition diagram for these modes. 2.1 active mode the active mode is the actual cpu running mode. instructions are read from the internal rom and executed by the cpu. leaving active mode via the halt instruction to go into standby mode, the sleep bit write to go into sleep mode or a reset from port a to go into reset mode. 2.2 standby mode executing a halt instruction puts the em6521 into standby mode. the voltage regulator, oscillator, watchdog timer, lcd, interrupts, timers and counters are operating. however, the cpu stops since the clock related to instruction execution stops. registers, ram and i/o pins retain their states prior to standby mode. standby is canceled by a reset or an interrupt request if enabled. 2.3 sleep mode writing to the sleep bit in the regsyscntl1 register puts the em6521 in sleep mode. the oscillator stops and most functions of the em6521 are inactive. to be able to write to the sleep bit, the sleepen bit in regsyscntl2 must first be set to "1". in sleep mode only the voltage regulator and the reset input are active. the ram data integrity is maintained. sleep mode may be canceled only by a high level of min 10s at the em6521 reset terminal or by the selected port a input reset combination, if option inpressleep is turned on. due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee stable oscillation. during sleep mode and the following start up the em6521 is in reset state. waking up from sleep clears the sleep flag but not the sleepen bit. inspecting the sleepen allows to determine if the em6521 was powered up ( sleepen = "0") or woken up from sleep ( sleepen = "1"). table 2.3.1. internal state in standby and sleep mode function standby sleep oscillator active stopped oscillator watchdog active stopped instruction execution stopped stopped interrupt functions active stopped registers and flags retained reset ram data retained retained option registers retained retained timer & counter active reset logic watchdog active reset i/o port b and serial port active high impedance, pulls as defined in option register input port a active no pull resistors and inputs deactivated except if inpressleep = "1" lcd active stopped (display off) strobe output active active buzzer output active high impedance voltage level detector finishes ongoing measure, then stop stopped reset pin active active figure 4 mode transition diagram active halt instruction sleep bit write irq standby sleep reset=1 reset=0 reset=1 reset=1 reset
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 8 3 power supply the em6521 is supplied by a single external power supply between v dd (vbat) and v ss (ground). a built-in voltage regulator generates vreg providing regulated voltage for the oscillator and the internal logic. the output drivers are supplied directly from the external supply v dd . the internal power configuration is shown below in figure 5. figure 5. internal power supply ref. logic terminal vreg terminal vbat ref. lcd all pad input & output buffers, svld, eeprom core logic,ram, lcd logic, oscillator voltage multiplier, lcd outputs m1b m1a 1kohm mvreg
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 9 4 reset figure 6. illustrates the reset structure of the em6521. one can see that there are six possible reset sources : (1) internal initial reset from the power on reset (por) circuitry. --> por (2) external reset from the reset terminal. --> system reset, reset cpu (3) external reset by simultaneous high/low inputs to port a. --> system reset, reset cpu (combinations are defined in the registers optinprsel1 and optinprsel2) (4) internal reset from the digital watchdog. --> system reset, reset cpu (5) internal reset from the oscillation detection circuit. --> system reset, reset cpu (6) internal reset when sleep mode is activated. --> system reset, reset cpu all reset sources activate the system reset and the reset cpu . the system reset delay ensures that the system reset remains active long enough for all system functions to be reset (active for n system clock cycles). the cpu reset delay ensures that the reset cpu remains active until the oscillator is in stable oscillation. as well as activating the system reset and the reset cpu, the por also resets all option registers and the sleep enable ( sleepen) latch. system reset and reset cpu do not reset the option registers nor the sleepen latch. reset state can be shown on strobe terminal by selecting strobeoutsel1,0 = 0 in reglcdcntl1 . figure 6. reset structure system reset delay cpu reset delay enable activate digital watchdog oscillation detection reset from port a input combination reset pad sleep optinprsleep reset cpu inhibit oscillation detection inhibit digital w atchdog por por to option registers & sleepen latch debounce sleep latch sleepen latch por internal data bus write reset read status write active read status ck[10] ck [ 1 ] ck[8] ck[1] ck[15] por analogue filter
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 10 4.1 oscillation detection circuit at power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry, and thus the system reset. the cpu of the em6521 remains in the reset state for the cpu reset delay, to allow the oscillator to stabilize after power up. the oscillator is disabled during sleep mode. so when waking up from sleep mode, the cpu of the em6521 remains in the reset state for the cpu reset delay, to allow the oscillator to stabilize. during this time, the oscillation detection circuit is inhibited. in active or standby modes, the oscillator detection circuit monitors the oscillator. if it stops for any reason, a system reset is generated. after clock restart the cpu waits for the cpu reset delay before executing the first instructions. the oscillation detection circuitry can be inhibited with bit nooscwd = 1 in register regvldcntl. at power up, and after any system reset, the function is activated. the cpu reset delay is 32768 system clocks ( ck[16] ) long. 4.2 reset terminal during active or standby modes the reset terminal has a debouncer to reject noise. reset must therefore be active for at least 16 ms (system clock = 32 khz). when canceling sleep mode, the debouncer is not active (no clock), however, reset passes through an analogue filter with a time constant of typical. 5s. in this case reset pin must be high for at least 10 s to generate a system reset. 4.3 input port a reset function by writing the optinprsel1 and optinprsel2 registers it is possible to choose any combination of port a input values to execute a system reset. the reset condition must be valid for at least 16ms (system clock = 32khz) in active and standby mode. optinprsleep selects the input port a reset function in sleep mode. if set to "1" the occurrence of the selected combination for input port a reset will immediately trigger a system reset (no debouncer) . reset combination selection ( inpreset) is done with registers optinprsel1 and optinprsel2. following formula is applicable : inprespa = inprespa[0] ? inprespa[1] ? inprespa[2] ? inprespa[3] inpres1pa[n] inpres2pa[n] inprespa[n] 00v ss 0 1 pa[n] 1 0 not pa[n] 11v dd n = 0 to 3 i.e. ; - no reset if inprespa[n] = v ss . - don't care function on a single bit with its inprespa[n] = v dd . - always reset if inprespa[3:0] = 'b1111 figure 7. input port a reset structure 0 1 mux 2 3 1 0 v ss pa[3] pa[3] v dd bit [0] bit [1] bit [2] bit [3] inprespa inprespa[3] inpres2pa[3] inpres1pa[3] input port a reset bit[2] selection input port a reset bit[1] selection input port a reset bit[0] selection input port a reset bit[3] selection input reset from port a
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 11 4.4 digital watchdog timer reset the digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of ck[1]. it will generate a system reset if it is not periodically cleared. the watchdog timer function can be inhibited by activating an inhibit digital watchdog bit ( nologicwd ) located in regvldcntl . at power up, and after any system reset, the watchdog timer is activated. if for any reason the cpu stops, then the watchdog timer can detect this situation and activate the system reset signal. this function can be used to detect program overrun, endless loops, etc. for normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 khz), or a system reset signal is generated. the watchdog timer is reset by writing a 1 to the wdreset bit in the timer. this resets the timer to zero and timer operation restarts immediately. when a 0 is written to wdreset there is no effect. the watchdog timer operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode for more than 2.5 seconds. from a system reset state, the watchdog timer will become active after 3.5 seconds. however, if the watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. it is therefore recommended to use the prescaler irqhz1 interrupt to periodically reset the watchdog every second. it is possible to read the current status of the watchdog timer in regsyscntl2 . after watchdog reset, the counting sequence is (on each rising edge of ck[1]) : 00, 01, 10, 11 { wdval1 wdval0 }. when going into the 11 state, the watchdog reset will be active within ? second. the watchdog reset activates the system reset which in turn resets the watchdog. if the watchdog is inhibited its timer is reset and therefore always reads 0. table 4.4.1 watchdog timer register regsyscntl2 bit name reset r/w description 3 wdreset 0 r/w reset the watchdog 1 -> resets the logic watchdog 0 -> no action the read value is always '0' 2 sleepen 0 r/w see operating modes (sleep) 1 wdval1 0 r watchdog timer data ck[1] divided by 4 0 wdval0 0 r watchdog timer data ck[1] divided by 2 4.5 cpu state after reset reset initializes the cpu as shown in table 4.5.1 below. table 4.5.1 initial cpu value after reset. name bits symbol initial value program counter 0 12 pc0 hex 000 (as a result of jump 0) program counter 1 12 pc1 undefined program counter 2 12 pc2 undefined stack pointer 2 sp psp[0] selected index register 7 ix undefined carry flag 1 cy undefined zero flag 1 z undefined halt 1 halt 0 instruction register 16 ir jump 0 periphery registers 4 reg. see peripheral memory map
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 12 5 oscillator and prescaler 5.1 oscillator a built-in crystal oscillator generates the system operating clock for the cpu and peripheral blocks, from an externally connected crystal (typically 32.768khz). the oscillator circuit is supplied by the regulated voltage, vreg. in sleep mode the oscillator is stopped. ems special design techniques guarantee the low current consumption of this oscillator. the external impedance between the oscillator pads must be greater than 10mohm. connection of any other components to the two oscillator pads must be confirmed by em microelectronic-marin sa. 5.2 prescaler the prescaler consists of fifteen elements divider chain which delivers clock signals for the peripheral circuits such as timer/counter, buzzer, lcd voltage multiplier, debouncer and edge detectors, as well as generating prescaler interrupts. the input to the prescaler is the system clock signal. power on initializes the prescaler to hex(0001). table 5.2.1 prescaler clock name definition function name 32 khz xtal function name 32 khz xtal system clock ck[16] 32768 hz system clock / 256 ck[8] 128 hz system clock / 2 ck[15] 16384 hz system clock / 512 ck[7] 64 hz system clock / 4 ck[14] 8192 hz system clock / 1024 ck[6] 32 hz system clock / 8 ck[13] 4096 hz system clock / 2048 ck[5] 16 hz system clock/ 16 ck[12] 2048 hz system clock / 4096 ck[4] 8 hz system clock / 32 ck[11] 1024 hz system clock / 8192 ck[3] 4 hz system clock / 64 ck[10] 512 hz system clock / 16384 ck[2] 2 hz system clock / 128 ck [9] 256 hz system clock / 32768 ck[1] 1 hz table 5.2.2 control of prescaler register regpresc bit name reset r/w description 3 pwmon 0 r/w see 10 bit counter 2 respresc 0 r/w write reset prescaler 1 -> resets the divider chain from ck[14] down to ck[2], sets ck[1]. 0 -> no action. the read value is always '0' 1 printsel 0 r/w interrupt select. 0 -> interrupt from ck[4] 1 -> interrupt from ck[6] 0 debsel 0 r/w debouncer clock select. 0 -> debouncer with ck[8] 1 -> debouncer with ck[11] or ck[14], see below with debsel = 1 one may choose either the ck[11] or ck[14] debouncer frequency by selecting the corresponding metal mask option (for rom version only). relative to 32khz the corresponding max. debouncer times are then 2 ms or 0.25 ms. for the metal mask selection refer to chapter 18.1.5. switching the printsel may generate an interrupt request. avoid it with maskirq32/8 = 0 selection during the switching operation. figure 8. prescaler frequency timing system clock ck[16] ck[15] ck[14] horizontal scale change ck[2] ck[1] first positive edge of 1 hz clock is 1s after the falling reset edge prescaler reset
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 13 the prescaler contains 3 interrupt sources: - irq32/8 ; this is ck[6] or ck[4] positive edge interrupt, the selection is depending on bit printsel. - irqhz1 ; this is ck[1] positive edge interrupt - irqblink ; this is 3/4 of ck[1] period interrupt there is no interrupt generation on reset. the first irqhz1 interrupt occurs 1 sec (32khz) after reset. a possible application for the irqblink is lcd-display blinking control together with irqhz1. figure 9. prescaler interrupts ck[2] irqblink irq hz1 ck[1]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 14 6 input and output ports the em6521 has: - one 4-bit input port ( port a ) - one 4-bit input/output port. ( port b ) - one serial interface (port sp) also configurable as 4-bit i/o port pull resistors can be added to all this ports with metal (rom version only) and/or register options. 6.1 ports overview table 6.1.1 input and output ports overview port mode mask(m:) or register(r:) option function bit-wise multifunction on ports pa [3:0] input m: pull-up m: pull-down (default) r: pull(up/down) select r: debouncer or direct input for irq requests and counter r: + or - for irq-edge and counter r: input reset combination -input -bit-wise interrupt request -software test variable conditional jump -pa[3],pa[0] input for the event counter -pa[3] input for the millisecond counter -port a reset inputs pa[3] 10 bit event counter clock start/stop of msc pa[2] - - pa[1] - - pa[0] 10 bit event counter clock - pb [3:0] individual input or output r: cmos or nch. open drain output r: pull-down on input r: pull-up on input -input or output -pb[3] for the pwm output -pb[2:0] for the ck[16,11,1] output -tristate output pb[3] pwm output pb[2] ck[16] output pb[1] ck[11] output pb[0] ck[1] output ps [3:0] serial i/o or port-wise input / output r: cmos or nch open drain output r: pull-down on input r: pull-up on input -psp[3], serial clock out -psp[2], serial data out -psp[1], serial status out -psp[0], serial data in -psp[3:0] 4-bit input/output -tristate output psp[3] serial clock output sclk psp[2] serial data output sout psp[1] ready or cs ready/cs psp[0] serial data input sin
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 15 6.2 port a the em6521 has one four bit general purpose cmos input port. the port a input can be read at any time, internal pull-up or pull-down resistors can be chosen by metal mask (for rom version only). all selections concerning port a are bit-wise executable. i.e. pull-up on pa[2], pull-down on pa[0], positive irq edge on pa[0] but negative on pa[1], etc. in sleep mode the port a pull-up or pull-down resistors are turned off, and the inputs are deactivated except if the inpressleep bit in the option register optfsel is set to 1. in this case the port a inputs are continuously monitored to match the input reset condition which will immediately wake the em6521 from sleep mode (all pull resistors remain). figure 10. input port a configuration intedgpa[n]=0 nodebintpa[n]=1 mask opt mpapu[n] pa3 for the millisecond counter irqpa[3:0] pa[n]terminal pa0, pa3 for 10-bit counter mask opt mpapd[n] debouncer p testvar ck[8] ck[11] or ck[14] db[3:0] nopullpa[n] vbat (v dd ) v ss input reset allowed when in sleep sleep 6.2.1 irq on port a for interrupt request generation (irq) one can choose direct or debouncer input and positive or negative edge irq triggering. with the debouncer selected ( optdebintpa ) the input must be stable for two rising edges of the selected debouncer clock ( regpresc ). this means a worst case of 16 ms (default) or 2 ms (0.25 ms by metal mask, for rom version only) with a system clock of 32 khz. either a positive or a negative edge on the port a inputs - after debouncer or not - can generate an interrupt request. this selection is done in the option register optintedgpa. all four bits of port a can provide an irq, each pin with its own interrupt mask bit in the regirqmask1 register. when an irq occurs, inspection of the regirq1 , regirq2 and regirq3 registers allows the interrupt to be identified and treated. at power on or after any reset the regirqmask1 is set to 0, thus disabling any input interrupt. a new interrupt is only stored with the next active edge after the corresponding interrupt mask is cleared. see also the interrupt chapter 10. it is recommended to mask the port a irqs while one changes the selected irq edge. else one may generate a irq (software irq). i.e. pa[0] on 0 then changing from positive to negative edge selection on pa[0] will immediately trigger an irqpa[0] if the irq was not masked.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 16 6.2.2 pull-up or pull-down each of the input port terminals pa[3:0] has a resistor integrated which can be used either as pull-up or pull- down resistor, depending on the selected metal mask options( rom version only). see the port a metal mask chapter for details. the pull resistor can be inhibited using the nopullpa[n] bits in the register optnopullpa. table 6.2.1. pull-up or pull-down resistor on port a inputs option mask pull-up mpapu[n] option mask pull-down mpapd[n] nopullpa[n] value action no no x no pull-up, no pull-down no yes 0 no pull-up, pull-down no yes 1 no pull-up, no pull-down yes no 0 pull-up, no pull-down yes no 1 no pull-up , no pull-down yes yes x not allowed* * only pull-up or pull-down may be chosen on any port a terminal (one choice is excluding the other) 6.2.3 software test variables the port a terminals pa[2:0] are also used as input conditions for conditional software branches. independent of the optdebintpa and the optintedgpa. these cpu inputs always have a debouncer. - debounced pa[0] is connected to cpu testvar1. - debounced pa[1] is connected to cpu testvar2. - debounced pa[2] is connected to cpu testvar3. 6.2.4 port a for 10-bit counter and msc the pa[0] and pa[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode. as for the irq generation one can choose debouncer or direct input with the register optdebintpa and non- inverted or inverted input with the register optintedgpa . debouncer input is always recommended. pad input pa[3] is also used as start/stop control for the millisecond counter. this control signal is derived from pa[3], it is independent of the port a debouncer and edge selection. refer also to figure 10. 6.3 port a registers table 6.3.1 register regpa bit name reset r/w description 3 padata[3] - r* pa[3] input status 2 padata[2] - r* pa[2] input status 1 padata[1] - r* pa[1] input status 0 padata[0] - r* pa[0] input status * direct read on port a terminals with n=03
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 17 table 6.3.2 register regirqmask1 bit name reset r/w description 3 maskirqpa[3] 0 r/w interrupt mask for pa[3] input 2 maskirqpa[2] 0 r/w interrupt mask for pa[2] input 1 maskirqpa[1] 0 r/w interrupt mask for pa[1] input 0 maskirqpa[0] 0 r/w interrupt mask for pa[0] input default "0" is: interrupt request masked, no new request stored table 6.3.3 register regirq1 bit name reset r/w description 3 irqpa[3] 0 r/w* interrupt request on pa[3] 2 irqpa[2] 0 r/w* interrupt request on pa[2] 1 irqpa[1] 0 r/w* interrupt request on pa[1] 0 irqpa[0] 0 r/w* interrupt request on pa[0] *; write "1" clears the bit, write "0" has no action, default "0" is: no interrupt request table 6.3.4 register optintedgpa bit name power on value r/w description 3 intedgpa[3] 0 r/w interrupt edge select for pa[3] 2 intedgpa[2] 0 r/w interrupt edge select for pa[2] 1 intedgpa[1] 0 r/w interrupt edge select for pa[1] 0 intedgpa[0] 0 r/w interrupt edge select for pa[0] default "0" is: positive edge selection table 6.3.5 register optdebintpa bit name power on value r/w description 3 nodebintpa[3] 0 r/w interrupt debounced for pa[3] 2 nodebintpa[2] 0 r/w interrupt debounced for pa[2] 1 nodebintpa[1] 0 r/w interrupt debounced for pa[1] 0 nodebintpa[0] 0 r/w interrupt debounced for pa[0] default "0" is: debounced inputs for interrupt generation table 6.3.6 register optnopullpa bit name power on value r/w description 3 nopullpa[3] 0 r/w pull-up/down selection on pa[3] 2 nopullpa[2] 0 r/w pull-up/down selection on pa[2] 1 nopullpa[1] 0 r/w pull-up/down selection on pa[1] 0 nopullpa[0] 0 r/w pull-up/down selection on pa[0] default "0" depending on mask selection
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 18 6.4 port b the em6521 has one four bit general purpose i/o port. each bit can be configured individually by software for input/output, pull-up, pull-down and cmos or nch. open drain output type. the port outputs either data, frequency or pwm signals. 6.4.1 input / output mode each port b terminal is bit-wise bi-directional. the input or output mode on each port b terminal is set by writing the corresponding bit in the regpbcntl control register. to set for input (default), 0 is written to the corresponding bit of the regpbcntl register which results in a high impedance state for the output driver. the output mode is set by writing 1 in the control register, and consequently the output terminal follows the status of the bits in the regpbdata register. the port b terminal status can be read on address regpbdata even in output mode. be aware that the data read on port b is not necessary of the same value as the data stored on regpbdata register. see also figure 11 for details. figure 11. port b architecture open drain option register port b direction register port b data register internal data bus mux active pull-down i / o terminal pb[n] ddr[n] dr[n] db[n] read read for pb[3:0] multiplexed output multiplexed output active multiplexed outputs are: pwm, ck[16], ck[11], ck[1] port b control active pull-up in nch. open drain mode read pd[n] pull-down option register od[n] mask option mpbpd[n] mask option mpbpd[n] 4
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 19 6.4.2 pull-up or pull-down on each terminal of pb[3:0] an internal input pull-up (metal mask mpbpu[n]) or pull-down (metal mask mpbpd[n]) resistor can be connected per metal mask option (rom version only). per default the two resistors are in place. in this case one can chose per software to have either a pull-up, a pull-down or no resistor. see below. for metal mask selection and available resistor values refer to chapter 0. pull-down on : mpbpd[n] must be in place , and bit nopdpb [n] must be 0 . pull-down off : mpbpd[n] is not in place, or if mpbpd[n] is in place nopdpb [n] = 1 cuts off the pull-down. or selecting nchopdpb [n] = 1 cuts off the pull-down. pull-up on * : mpbpu[n] must be in place, and bit nchopdpb [n] must be 1 , and (bit pbiocntl[n] = 0 (input mode) or if pbiocntl[n] = 1 while pbdata [n] = 1. ) pull-up off* : mpbpu[n] is not in place, or if mpbpu[n] is in place nchopdpb [n] = 0 cuts off the pull-up, or if mpbpu[n] is in place and if nchopdpb [n] = 1 then pbdata [n] = 0 cuts off the pull-up. never pull-up and pull-down can be active at the same time. for power saving one can switch off the port b pull resistors between two read phases. no cross current flows in the input amplifier while the port b is not read. the recommended order is : switch on the pull resistor. allow sufficient time - rc constant - for the pull resistor to drive the line to either v ss or v dd . read the port b switch off the pull resistor minimum time with current on the pull resistor is 4 system clock periods, if the rc time constant is lower than 1 system clock period. adding a nop instruction before reading moves the number of periods with current in the pull resistor to 6 and the maximum rc delay to 3 clock periods. 6.4.3 cmos / nch. open drain output the port b outputs can be configured as either cmos or nch. open drain outputs. in cmos both logic 1 and 0 are driven out on the terminal. in nch. open drain only the logic 0 is driven on the terminal, the logic 1 value is defined by the internal pull-up resistor (if implemented), or high impedance. figure 12. cmos or nch. open drain outputs i / o term inal pb[n] mux active pullup for high state dr[n] frequency outputs tri-state output buffer : high im pedance for data = 1 i / o term inal pb[n] mux dr[n] frequency outputs tri-state output buffer : closed data 1 cmos output nch. open drain output
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 20 6.4.4 pwm and frequency output pb[3] can also be used to output the pwm (pulse width modulation) signal from the 10-bit counter, the ck[16], ck[11] as well as the ck[1] prescaler frequencies. -selecting pwm output on pb[3] with bit pwmon in register regpresc and running the counter. -selecting ck[16] output on pb[2] with bit pb32khzout in register optfselpb -selecting ck[11] output on pb[1] with bit pb1khzout in register optfselpb -selecting ck[1 ] output on pb[0] with bit pb1hzout in register optfselpb 6.5 port b registers table 6.5.1 register regpbdata bit name reset r/w description 3 pbdata[3] - r*/w pb[3] input and output 2 pbdata[2] - r*/w pb[2] input and output 1 pbdata[1] - r*/w pb[1] input and output 0 pbdata[0] - r*/w pb[0] input and output * : direct read on the port b terminal (not the internal register) table 6.5.2 register regpbcntl bit name reset r/w description 3 pbiocntl[3] 0 r/w i/o control for pb[3] 2 pbiocntl[2] 0 r/w i/o control for pb[2] 1 pbiocntl[1] 0 r/w i/o control for pb[1] 0 pbiocntl[0] 0 r/w i/o control for pb[0] default "0" is: port b in input mode table 6.5.3 option register optfselpb bit name power on value r/w description 3 inpressleep 0 r/w reset from sleep with port a 2 pb32khzout 0 r/w ck[16] output on pb[2] 1 pb1khzout 0 r/w ck[11] output on pb[1] 0 pb1hzout 0 r/w ck[1] output on pb[0] default "0" is: no frequency output, port a input reset can not reset the sleep mode. table 6.5.4 option register optnopdpb bit name power on value r/w description 3 nopdpb[3] 0 r/w no pull-down on pb[3] 2 nopdpb[2] 0 r/w no pull-down on pb[2] 1 nopdpb[1] 0 r/w no pull-down on pb[1] 0 nopdpb[0] 0 r/w no pull-down on pb[0] default "0" is: pull-down on table 6.5.5 option register optnchopdpb bit name power on value r/w description 3 nchopdpb[3] 0 r/w nch. open drain on pb[3] 2 nchopdpb[2] 0 r/w nch. open drain on pb[2] 1 nchopdpb[1] 0 r/w nch. open drain on pb[1] 0 nchopdpb[0] 0 r/w nch. open drain on pb[0] default "0" is: cmos output
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 21 6.6 port serial the em6521 contains a simple, half duplex three wire synchronous type serial interface., which can be used to program or read an external eeprom, adc, ... etc. for data reception, a shift-register converts the serial input data on the sin(psp[0]) terminal to a parallel format, which is subsequently read by the cpu in registers regsdatal and regsdatah for low and high nibble. to transmit data, the cpu loads data into the shift register, which then serializes it on the sout(psp[2]) terminal. it is possible for the shift register to simultaneously shift data out on the sout terminal and shift data on the sin terminal. in master mode, the shifting clock is supplied internally by the prescaler : one of three prescaler frequencies are available, ck[16], ck[15] or ck[14]. in slave mode, the shifting clock is supplied externally on the sclkin(psp[3]) terminal. in either mode, it is possible to program : the shifting edge, shift msb first or lsb first and direct shift output. all these selection are done in register regscntl1 and regscntl2 . the psp[3..0] terminal configuration is shown in figure 14. when the serial interface is active then : * psp[1] {ready / cs) is outputting the ready (slave mode) or the cs signal (master mode). * psp[2] {sout} is always an output. * psp[0] {sin} is always an input. * psp[3] {sclk} is an output for master mode {sclkout} and an input for slave mode {sclkin} 6.6.1 4-bit parallel i/o selecting om[1],om[0] = 1 in register regscntl2 the psp[3:0] terminals are configured as a 4-bit output. output data is stored in the register regspdata . the regspdata is defined as a read/write register, but what is read is not the register output, but the port psp[3:0] terminal values selecting om[1],om[0] = 0 in register regscntl2 the psp[3:0] outputs are cut off (tristate). the terminals can be used as inputs with individual (bit-wise) pull-up or pull-down settings. independent of the selected configuration, the psp[3:0] terminal levels are always readable. figure 13. serial interface architecture shift complete (8th shift clock) 8 bit shift register serial input data from sin terminal irqserial serial output data to sout terminal serial master clock output sclkout to sclk terminal internal master clock source (from prescaler) m u x external slave clock source (sclkin from sclk terminal) mode start direct msb/lsb status shift first control logic clock enable shift ck status to cs/ ready terminal control & status registers reset start write read tx rx 4-bit internal data bus high-z to all sp[3:0] terminals
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 22 6.6.2 pull-up or pull-down for each terminal of psp[3:0] an input pull-up (metal mask mpspu[n]) or pull-down (metal mask mpspd[n]) resistor can be implemented per metal mask option (rom version only). per default the two metal masks are in place, so one can chose per software to have either a pull-up, a pull-down or no resistor. for metal mask selection and available resistor values refer to chapter erreur! source du renvoi introuvable. pull-down on : mpspd[n] must be in place , and the bit nopdps [n] must be 0 . pull-down off : mpspd[n] is not in place, or if mpspd[n] is in place nopdps [n] = 1 cuts off the pull-down. or selecting nchopdps [n] = 1 cuts off the pull-down. pull-up on * : mpspu[n] must be in place, and the bit nchopdps [n] must be 1 , and ( the bits om[1,0] in regsyscntl2 = 00 (input mode) or any of the port sp terminals is in output mode with a logic 1 to be driven) . pull-up off* : mpspu[n] is not in place, or if mpspu[n] is in place nchopdps [n] = 0 cuts off the pull-up, or if mpspu[n] is in place and nchopdps [n] = 1 then serpdata [n] = 0 cuts off the pull-up. figure 14. port sp terminal configuration internal data bus mux dr[n] db [ n ] read read or serial mode serial interface outputs ( sout , ready/cs and sclk ) parallel output serial / parallel control read pd[n] pull-down option register od[n] nch. open drain option register mode (direction for sclk out terminal only) tristate parallel output data register serial interface inputs ( sin and sclk in) active pulldown i / o terminal sp[n] active pull-up in nch. open drain mode mask option mpspd[n] mask option mpspu[n]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 23 for power saving one can switch off the port sp pull resistors between two read phases. no cross current flows in the input amplifier while the port sp is not read. this power saving feature must only be used in tristate mode (om[0,1]=0). the recommended order is : switch on the pull resistor. allow sufficient time - rc constant - for the pull resistor to drive the line to either v ss or v dd . read the port sp switch off the pull resistor minimum time with current on the pull resistor is 4 periods of the system clock, if the rc constant is lower than 1 system clock period. adding a nop before reading moves the number of periods with current in the pull resistor to 6 and the maximum rc delay to 3 clock periods. 6.6.3 nch. open drain outputs the port sp outputs can be configured as either cmos or nch. open drain outputs. in cmos both logic 1 and 0 are driven out on the terminal. in nch. open drain only the logic 0 is driven out on the terminal, the logic 1 value is high impedance or defined by the internal pull-up resistor (if existing). 6.6.4 general functional description after power on or after any reset the serial interface is in serial slave mode with start and status set to 0, lsb first, negative shift edge and all outputs are in high impedance state. when the start bit is set, the shift operation is enabled and the serial interface is ready to transmit or receive data, eight shift operations are performed: 8 serial data values are read from the data input terminal into the shift register and the previous loaded 8-bits are send out via the data output terminal. after the eight shift operation, an interrupt is generated, and the start bit is reset. parallel to serial conversion procedure ( master mode example ). write to regscntl1 serial control (clock freq. in master mode, edge and msb/lsb select). write to regsdatal and regsdatah (shift out data values). write to regscntl2 (start=1, mode select, status). ---> starts the shift out after the eighth clock an interrupt is generated, start becomes low. then, interrupt handling serial to parallel conversion procedure (slave mode example). write to regscntl1 (slave mode, edge and msb/lsb select). write to regscntl2 (start=1, mode select, status). after eight serial clocks an interrupt is generated, start becomes low. interrupt handling. shift register regsdatal and regsdatah read. a new shift operation can be authorized. figure 15. cmos or nch. open drain outputs i / o terminal sp[n] mux active pull-up for high state dr[n] serial interface output tristate output buffer : high impedance for data = 1 data i / o terminal sp[n] mux dr[n] serial interface output tristate output buffer : closed data 1 cmos output nch. open drain output
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 24 6.6.5 detailed functional description master or slave mode is selected in the control register regscntl1. in slave mode, the serial clock comes from an external device and is input via the psp[3] terminal as a synchronous clock (sclkin) to the serial interface. the serial clock is ignored as long as the start bit is not set. after setting start, only the eight following active edges of the serial clock input psp[3] are used to shift the serial data in and out. after eight serial clock edges the start bit is reset. the psp[1] terminal is a copy of the ( start or status) bit values, it can be used to indicate to the external master, that the interface is ready to operate or it can be used as a chip select signal in case of an external slave. in master mode, the synchronous serial clock is generated internally from the system clock. the frequency is selected from one out of three sources ( ms0 and ms1 bits in regscntl1 ) . the serial shifting clock is only generated during start = high and is output to the sclk terminal as the master clock (sclkout). when start is low, the serial clock output on psp[3] is 0. an interrupt request irqserial is generated after the eight shift operations are done. this signal is set by the last negative edge of the serial interface clock on psp[3] (master or slave mode) and is reset to 0 by the next write of start or by any reset. this interrupt can be masked with register regirqmask3. for more details about the interrupt handling see chapter 10. serial data input on psp[0] is sampled by the positive or negative serial shifting clock edge, as selected by the control register posnneg bit . serial data input is shifted in lsb first or msb first, as selected by the control register msbnlsb bit . 6.6.6 output modes serial data output is given out in two different ways (refer also to figure 16 and figure 17). - om[1] = 1, om[0] = 0 : the serial output data is generated with the selected shift register clock ( posnneg ). the first data bit is available directly after the start bit is set. - om[1] = 0, om[0] = 1 : the serial output data is re-synchronized by the positive serial interface clock edge, independent of the selected clock shifting edge. the first data bit is available on the first positive serial interface clock edge after start=1. table 6.6.6 output mode selection in regscntl2 om[1] om[0] output mode description 0 0 tristate output disable (tristate on psp[3:0]) 01serial- synchronized re-synchronized positive edge data shift out 1 0 serial-direct direct shift pos. or neg. edge data out 1 1 parallel parallel port sp output tristate output is selected by default. figure 16. direct or re-synchronized output bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 sin sout +ve/-ve edge direct shift out bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 m u x bit4 bit5 bit6 bit7 bit0 bit[n ] bit1 bit2 bit3 +ve edge clock sin sout +ve/-ve edge re-synchronised shift out m u x bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 msbnlsb
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 25 6.6.7 reset and sleep on port sp during circuit initialization, all option registers are reset by power on reset and therefore all pull-ups are off and all pull-downs are on. during sleep mode, port sp inputs are cut-off , the circuit is in reset state. however the reset state does not reset the option registers and pull-downs, if previously turned on, remain on even during sleep mode. after any reset the serial interface parameters are reset to : slave mode, start and status = 0, lsb first, negative edge shift , psp[3:0] tristate. note : a write operation in the control registers or in the data registers while start is high will change internal values and may cause an error condition. the user must take care of the serial interface status before writing internal registers. in order to read the correct values on the data registers, the shift operation must be halted during the read accesses. figure 17 shift operation and irq generation sclk = system clock; active edge = neg. edge; sense = msb first clock source shift ck start irq shift r eg i s t e r sin om[1]=1, om[0]=0 : direct data out on pos. or neg. sclk clock edge depending on bit posnneg sout om[1]=0, om[0]=1 : re-synchronized on positive sclk clock edge data out sout 10010011 01001100 011 0 0 1 0 1 1 0 0 1 1 0 0 0 011 0 0 1 0 1 figure 18. sample basic serial port connections optional connection external em6521 sp[2]; sout sp[3]; sclkin sp[0]; sin sp[1]; status serial data in serial clock out serial data out ready external em6521 sp[2]; sout sp[3]; sclkout sp[0]; sin ready sp[1]: status serial data in serial clock in serial data out status output cs slave mode master mode
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 26 6.7 serial interface registers table 6.7.1 register regscntl1 bit name reset r/w description 3 ms1 0 r/w frequency selection 2 ms0 0 r/w frequency selection 1 posnneg 0 r/w positive or negative clock edge selection for shift operation 0 msbnlsb 0 r/w shift msb or lsb value first default "0" is: slave mode external clock, negative edge, lsb first table 6.7.2 frequency and master slave mode selection ms1 ms0 description 0 0 slave mode: clock from external 0 1 master mode: system clock / 4 1 0 master mode: system clock / 2 1 1 master mode: system clock table 6.7.3 register regscntl2 bit name reset r/w description 3 start 0 r/w enabling the interface, 2 status 0 r/w ready or chip select output on psp[1] 1 om[1] 0 r/w output mode select 1 0 om[0] 0 r/w output mode select 0 default "0" is: interface disabled, status 0, serial mode, output tristate. table 6.7.4 register regsdatal bit name reset r/w description 3 serdatal[3] 0 r/w serial data low nibble 2 serdatal[2] 0 r/w serial data low nibble 1 serdatal[1] 0 r/w serial data low nibble 0 serdatal[0] 0 r/w serial data low nibble default "0" is: data equal 0. table 6.7.5 register regsdatah bit name reset r/w description 3 serdatah[3] 0 r/w serial data high nibble 2 serdatah[2] 0 r/w serial data high nibble 1 serdatah[1] 0 r/w serial data high nibble 0 serdatah[0] 0 r/w serial data high nibble default "0" is: data equal 0.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 27 table 6.7.6 register regspdata bit name reset r/w description 3 serpdata[3] 0 r* /w parallel output data 2 serpdata[2] 0 r* /w parallel output data 1 serpdata[1] 0 r* /w parallel output data 0 serpdata[0] 0 r* /w parallel output data r* : the input terminal value is read, not the register table 6.7.7 option register optnopdps bit name r/w description 3 nopdps[3] 0 r/w no pull-down on psp[3] 2 nopdps[2] 0 r/w no pull-down on psp[2] 1 nopdps[1] 0 r/w no pull-down on psp[1] 0 nopdps[0] 0 r/w no pull-down on psp[0] default "0" is: pull-down on table 6.7.8 option register optnchopdps bit name r/w description 3 nchopdps[3] 0 r/w nch. open drain on psp[3] 2 nchopdps[2] 0 r/w nch. open drain on psp[2] 1 nchopdps[1] 0 r/w nch. open drain on psp[1] 0 nchopdps[0] 0 r/w nch. open drain on psp[0] default "0" is: cmos output
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 28 7 melody, buzzer a normal application is to drive a buzzer connected onto the terminal buzzer. this peripheral cell is a combination of a 7 frequency tone generator and a 4-bit timer, used to provide a 50% duty cycle signal on the buzzer terminal of a pre-selected length and frequency. the buzzer terminal is active as long as the timer is not 0 or the swbuzzer is set to 1. the 4-bit timer can be used for another application independent of the buzzer terminal by selecting "silence" instead of another frequency on the buzzer output. "silence" can also be used as part of a melody, or to switch off the buzzer. to use the buzzer independent of the 4-bit timer one has to set the switch swbuzzer. this bit is in register regmeltim and selects the signal duration on the buzzer output. if swbuzzer =1 then the signal is output until the bit is set back to 0 . with swbuzzer =0 the output signal duration is controlled by the 4bit timer. if neither the swbuzzer or the timer are active, the buzzer terminal is on 0. the high impedance state setting with bzouten is independent of the swbuzzer and timer settings. as soon as the bit is set to 1 the buzzer terminal is set tristate. see also figure 19. 7.1 4-bit timer the timer has 2 modes: - single run mode ( auto =0) - continuous run mode ( auto =1) mode selection and timer count down frequency is done in register regmeltim. all timer frequencies are coming from the prescaler. the 4-bit timer can be used independent of the melody buzzer application. whenever the timer reaches 0 it generates an interrupt request irqbz in the register regirq2 . this interrupt can be masked with the bit maskirqbz in register regirqmask2. by writing 0 into the timer period register the timer stops immediately and does not generate an interrupt. figure 19. melody generator block diagram ck[16] (from prescaler) close frequency select swbuzzer auto bzouten zero frequency generator 4 - bit timer bz terminal 8 flbuzzer irqbz control & status registers internal data bus db[3:0] timer clock (from prescaler) control logic period register v ss 0 1 mux
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 29 7.1.1 single run mode the timer duration is controlled by the regmelperi value and the selected timer frequency in regmeltim. the timer is counting down from its previously charged value until it reaches 0. on 0 the timer stops and generates an interrupt request. the buzzer frequency output is enabled after the next positive timer clock edge and remains enabled until the timer reaches 0. 7.1.2 continuos run mode this is almost the same as the single run mode only that in this case the timer after reaching 0 reloads itself automatically with the register regmelperi value. every time the timer reaches 0 an interrupt request is send. there are 2 ways to stop the continuos mode. first, changing the mode to single run mode. as the timer reaches 0 it stops. the last period after auto =0 is of length regmelperi + 1 . second, loading 0 into the timer period register regmelperi stops the timer immediately, no interrupt is generated and the auto flag is reset. the buzzer frequency output is enabled directly by writing auto =1. figure 20. single run mode 2 10 0 1 p writes 2 into regmelperi p writes 1 into regmelperi timer clock timer value buzzer irqbz figure 21. continuos run mode 2 21 0 1 2 0 0 1 p writes auto = 0 p writes auto = 1 p writes 2 into regmelperi timer clock n periods n+1 periods timer value buzzer irqbz
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 30 7.2 programming order single run mode usage 1st, selecting the buzzer frequency into regmelfsel . 2nd, selecting the timer clock frequency in regmeltim . 3rd, selecting the timer period in regmelperi . --> on the next positive clock edge the buzzer output is enabled. continuos run mode usage 1st, selecting the buzzer frequency into regmelfsel . 2nd, selecting the timer clock frequency in regmeltim ( auto =0). 3rd, selecting the timer period in regmelperi . 4th, set bit auto in regmeltim . --> immediately the buzzer output is active. avoid timer clock frequency switch during buzzer operation. 7.3 melody registers table 7.3.1 register regmelfsel bit name reset r/w description 3 bzouten 0 r/w buzzer output tristate 2 melfsel[2] 0 r/w buzzer frequency select 1 melfsel[1] 0 r/w buzzer frequency select 0 melfsel[0] 0 r/w buzzer frequency select default : buzzer tristate, silence table 7.3.2 buzzer output frequency selection with melfsel[2..0] melfsel[2] melfsel[1] melfsel[0] frequency 000v ss (silence) 001sysclock/8do8 0 1 0 sysclock/10 sol7# 0 1 1 sysclock/12 fa7 1 0 0 sysclock/14 re7 1 0 1 sysclock/16 do7 1 1 0 sysclock/20 sol6# 1 1 1 sysclock/24 fa6 table 7.3.3 register regmeltim bit name reset r/w description 3 swbuzzer flbuzzer 0 0 w r write: switch buzzer read: flag buzzer 2 auto 0 r/w single or continuos run mode 1 ftimsel1 0 r/w timer clock frequency select 0 ftimsel0 0 r/w timer clock frequency select default : single run mode, ck[3] from prescaler as timer clock
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 31 table 7.3.4 timer clock frequency select ftimsel0 ftimsel1 timer clock on 32 khz operation 0 0 ck[3] 4 hz 1 0 ck[5] 16 hz 0 1 ck[7] 64 hz 1 1 ck[1] 1 hz table 7.3.5 register regmelperi bit name reset r/w description 3 per[3] 0 w melody timer period msb 2 per[2] 0 w melody timer period 1 per[1] 0 w melody timer period 0 per[0] 0 w melody timer period lsb the total timer period duration is calculated as following: duration = value(regmelperi) x 1/ck[n] where, ck[n] is the timer clock frequency and value(regmelperi) is the value of the register regmelperi.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 32 8 10-bit counter the em6521 has a built-in universal cyclic counter. it can be configured as 10, 8, 6 or 4-bit counter. if 10-bits are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting. the counter works in up- or down count mode. eight clocks can be used as the input clock source, six of them are prescaler frequencies and two are coming from the input pads pa[0] and pa[3]. in this case the counter can be used as an event counter. the counter generates an interrupt request irqcount0 every time it reaches 0 in down count mode or 3ff in up count mode. another interrupt request irqcntcomp is generated in compare mode whenever the counter value matches the compare data register value. each of this interrupt requests can be masked (default). see section 10 for more information about the interrupt handling. a 10-bit data register creg[9:0] is used to initialize the counter at a specific value (load into count[9:0] ). this data register ( creg[9:0] ) is also used to compare its value against count[9:0] for equivalence. a pulse-width-modulation signal (pwm) can be generated and output on port b terminal pb[3]. 8.1 full and limited bit counting in full bit counting mode the counter uses its maximum of 10-bits length (default ). with the bitsel[1,0] bits in register regcdatah one can lower the counter length, for irq generation, to 8, 6 or 4 bits. this means that actually the counter always uses all the 10-bits, but irqcount0 generation is only performed on the number of selected bits. the unused counter bits may or may not be taken into account for the irqcomp generation depending on bit selintfull . refer to chapter 8.4. figure 22. 10-bit counter block diagram en comparator ck up/down up/down counter en evcount counter read register regcdatal, m, h (count[9:0]) regcdatal, m, h (creg[9:0]) load irqcntcomp pwm irqcount0 data register db[3:0] pa[0] ck[15] ck[12] ck[10] ck[8] ck[4] ck[1] pa[3] ck mux regccntl1, 2 countfsel2...0 up/down start evcount load encomp table 7.3.1. counter length selection bitsel[1] bitsel[0 ] counter length 0 0 10-bit 018-bit 106-bit 114-bit
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 33 8.2 frequency select and up/down counting 8 different input clocks can be selected to drive the counter. the selection is done with bits countfsel20 in register regccntl1 . 6 of this input clocks are coming from the prescaler. the maximum prescaler clock frequency for the counter is half the system clock and the lowest is 1hz. therefore a complete counter roll over can take as much as 17.07 minutes (1hz clock, 10 bit length) or as little as 977 m s (ck[15], 4 bit length). the irqcount0 , generated at each roll over, can be used for time bases, measurements length definitions, input polling, wake up from halt mode, etc. the irqcount0 and irqcomp are generated with the system clock ck[16] rising edge. irqcount0 condition in up count mode is : reaching 3ff if 10-bit counter length (or ff, 3f, f in 8, 6, 4-bit counter length). in down count mode the condition is reaching 0. the non-selected bits are dont care. for irqcomp refer to section 8.4. note: the prescaler and the microprocessor clocks are usually non-synchronous, therefore time bases generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode). however the prescaler clock can be synchronized with p commands using for instance the prescaler reset function. the two remaining clock sources are coming from the pa[0] or pa[3] terminals. refer to the figure 10 on page 15 for details. both sources can be either debounced (ck[11] or ck[8]) or direct inputs, the input polarity can also be chosen. the output after the debouncer polarity selector is named pa3 , pa0 respectively. for the debouncer and input polarity selection refer to chapter 6.3. in the case of port a input clock without debouncer, the counting clock frequency will be half the input clock on port a. the counter advances on every odd numbered port a negative edge ( divided clock is high level ). irqcount0 and irqcomp will be generated on the rising pa3 or pa0 input clock edge. in this condition the em6521 is able to count with a higher clock rate as the internal system clock (hi-frequency input). maximum port a input frequency is limited to 200khz (@v dd 3 2.0 v). if higher frequencies are needed, please contact em-marin. in both, up or down count (default) mode, the counter is cyclic. the counting direction is chosen in register regccntl1 bit up/down (default 0 is down count). the counter increases or decreases its value with each positive clock edge of the selected input clock source. start up synchronization is necessary because one can not always know the clock status when enabling the counter. with evcount=0, the counter will only start on the next positive clock edge after a previously latched negative edge, while the start bit was already set to 1. this synchronization is done differently if event count mode (bit evcount ) is chosen. refer also to figure 24. internal clock synchronization. figure 23. counter clock timing prescaler frequencies or debounced port a clocks non-debounced port a clocks (system clock independent) system clock prescaler clock counting counter irqs divided clock system clock port a clock counting c ounter ir q s
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 34 8.3 event counting the counter can be used in a special event count mode where a certain number of events (clocks) on the pa[0] or pa[3] input are counted. in this mode the counting will start directly on the next active clock edge on the selected port a input. the event count mode is switched on by setting bit evcount in the register regccntl2 to 1.pa[3] and pa[0] inputs can be inverted depending on register optintedgpa and should be debounced. the debouncer is switched on in register optdebintpa bits nodebintpa[3,0]=0. its frequency depends on the bit debsel from register regpresc setting. the inversion of the internal clock signal derived from pa[3] or pa[0] is active with intedgpa[3] respectively intedgpa[0] equal to 1. refer also to figure 10 for internal clock signal generation. 8.4 compare function a previously loaded register value ( creg[9:0] ) can be compared against the actual counter value ( count[9:0] ) . if the two are matching (equality) then an interrupt ( irqcomp ) is generated. the compare function is switched on with the bit encomp in the register regccntl2 . with encomp = 0 no irqcomp is generated. starting the counter with the same value as the compare register is possible, no irq is generated on start. full or limited bit compare are possible, defined by bit selintfull in register regsyscntl1 . encomp must be written after a load operation ( load = 1). every load operation resets the bit encomp. full bit compare function. bit selintfull is set to 1. the function behaves as described above independent of the selected counter length. limited bit counting together with full bit compare can be used to generate a certain amount of irqcount0 interrupts until the counter generates the irqcomp interrupt. with pwmon =1 the counter would have automatically stopped after the irqcomp, with pwmon =0 it will continue until the software stops it. encomp must be cleared before setting selintfull and before starting the counter again. be careful, pwmon also redefines the port b pb[3] output data.(refer to section 8.5). limited bit compare with the bit selintfull set to 0 (default) the compare function will only take as many bits into account as defined by the counter length selection bitsel[1:0] (see chapter 8.1). 8.5 pulse width modulation (pwm) the pwm generator uses the behavior of the compare function (see above) so encomp must be set to activate the pwm function.. at each roll over or compare match the pwm state - which is output on port b pb[3] - will toggle. the start value on pb[3] is forced while encomp is 0 the value is depending on the up or down count mode. every counter value load operation resets the bit encomp and therefore the pwm start value is reinstalled. setting pwmon to 1 in register regpresc routes the counter pwm output to port b terminal pb[3]. insure that pb[3] is set to output mode . refer to section 6.4 for the port b setup. the pwm signal generation is independent of the limited or full bit compare selection bit selintfull. however if selintfull = 1 (full) and the counter compare function is limited to lower than 10 bits one can generate a predefined number of output pulses. in this case, the number of output pulses is defined by the value of the unused counter bits. it will count from the start value until the irqcomp match. one must not use a compare value of hex 0 in up count mode nor a value of hex 3ff (or ff,3f, f if limited bit compare) in down count mode. figure 24. internal clock synchronization ck start count[9:0 ] + / - 1 + / - 1 evcount = 0 ck start evcount = 0 ck start evcount = 1 ck start evcount = 1 count[9:0 ] + / - 1 count[9:0 ] count[9:0 ]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 35 for instance, loading the counter in up count mode with hex 000 and the comparator with hex c52 which will be identified as : - bits[11:10] are limiting the counter to limits to 4 bits length, =03 (bitsel[1,0]) - bits [9:4] are the unused counter bits = hex 05 (bin 000101), (number of pwm pulses) - bits [3:0] (comparator value = 2). (length of pwm pulse) thus after 5 pwm-pulses of 2 clocks cycles length the counter generates an irqcomp and stops. the same example with selintfull=0 (limited bit compare) will produce an unlimited number of pwm at a length of 2 clock cycles. 8.5.1 how the pwm generator works. for up count mode ; setting the counter in up count and pwm mode the pb[3] pwm output is defined to be 0 ( encomp =0 forces the pwm output to 0 in upcount mode, 1 in downcount). each roll over will set the output to 1 and each compare match will set it back to 0. the compare match for pwm always only works on the defined counter length. this, independent of the selintfull setting which is valid only for the irq generation. refer also to the compare setup in chapter 8.4. in above example the pwm starts counting up on hex 0, 2 cycles later compare match -> pwm to 0, 14 cycles later roll over -> pwm to 1 2 cycles later compare match -> pwm to 0 , etc. until the completion of the 5 pulses. the normal irq generation remains on during pwm output. if no irqs are wanted, the corresponding masks need to be set. in down count mode everything is inverted. the pwm output starts with the 1 value. each roll over will set the output to 0 and each compare match will set it back to 1. for limited pulse generation one must load the complementary pulse number value. i.e. for 5 pulses counting on 4 bits load bits[9 :4] with hex 3a (bin 111010). 8.5.2 pwm characteristics pwm resolution is : 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps) the minimal signal period is : 16 (4-bit) x fmax* -> 16 x 1/ck[15] -> 977 s (32 khz) the maximum signal period is : 1024 x fmin* -> 1024 x 1/ck[1] -> 1024 s (32 khz) the minimal pulse width is : 1 bit -> 1 x 1/ck[15] -> 61 s (32 khz) * this values are for fmax or fmin derived from the internal system clock (32khz). much shorter (and longer) pwm pulses can be achieved by using the port a as frequency input. one must not use a compare value of hex 0 in up count mode nor a value of hex 3ff (or ff,3f, f if limited bit compare) in downcount mode. figure 25. pwm output in up count mode data+2 data+1 data-1 dat a ... 001 000 03f 03e pwm output irqcomp irqcount0 compare roll-over count[9 :0] clock figure 26. pwm output in down count mode data-2 data-1 data+1 data ... 3f e 3ff 000 001 pwm output irqcomp irqcount0 compare roll-over count[9 :0] clock
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 36 8.6 counter setup regcdatal[3:0], regcdatam[3:0], regcdatah[1:0] are used to store the initial count value called creg[9:0] which is written into the count register bits count[9:0] when writing the bit load to 1 in regccntl2 . this bit is automatically reset thereafter. the counter value count[9:0] can be read out at any time, except when using non-debounced high frequency port a input clock. to maintain data integrity the lower nibble count[3:0] must always be read first. the shcount[9:4] values are shadow registers to the counter. to keep the data integrity during a counter read operation (3 reads), the counter values [9:4] are copied into these registers with the read of the count[3:0] register. if using non-debounced high frequency port a input the counter must be stopped while reading the count[3:0] value to maintain the data integrity. in down count mode an interrupt request irqcount0 is generated when the counter reaches 0. in up count mode, an interrupt request is generated when the counter reaches 3ff (or ff,3f,f if limited bit counting). never an interrupt request is generated by loading a value into the counter register. when the counter is programmed from up into down mode or vice versa, the counter value count[9:0] gets inverted. as a consequence, the initial value of the counter must be programmed after the up/down selection. loading the counter with hex 000 is equivalent to writing stop mode, the start bit is reset, no interrupt request is generated. how to use the counter; if pwm output is required one has to put the port b[3] in output mode and set pwmon=1 in step 5. 1st, set the counter into stop mode ( start =0). 2nd, select the frequency and up- or down count mode in regccntl1. 3rd, write the data registers regcdatal, regcdatam, regcdatah (counter start value and length) 4th, load the counter, load =1, and choose the mode. ( evcount , encomp =0) 5th, select bits pwmon in regpresc and selintfull in regsyscntl1 6th, if compare mode desired , then write regcdatal, regcdatam, regcdatah (compare value) 7th, set bit start and select encomp in regccntl2 8.7 10-bit counter registers table 8.7.1 register regccntl1 bit name reset r/w description 3 up/down 0 r/w up or down counting 2 countfsel2 0 r/w input clock selection 1 countfsel1 0 r/w input clock selection 0 countfsel0 0 r/w input clock selection default : pa0 ,selected as input clock, down counting table 8.7.2 counter input frequency selection with countfsel[2..0] countfsel2 countfsel1 countfsel0 clock source selection 0 0 0 port a pa[0] 0 0 1 prescaler ck[15] 0 1 0 prescaler ck[12] 0 1 1 prescaler ck[10] 1 0 0 prescaler ck[8] 1 0 1 prescaler ck[4] 1 1 0 prescaler ck[1] 1 1 1 port a pa[3]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 37 table 8.7.3 register regccntl2 bit name reset r/w description 3 start 0 r/w start/stop control 2 evcount 0 r/w event counter enable 1 encomp 0 r/w enable comparator 0 load 0 r/w write: load counter register; read: always 0 default : stop, no event count, no comparator, no load table 8.7.4 register regsyscntl1 bit name reset r/w description 3 inten 0 r/w general interrupt enable 2 sleep 0 r/w sleep mode 1 selintfull 0 r/w compare interrupt select 0 chtmdis 0 r/w for em test only default : interrupt on limited bit compare table 8.7.5 register regcdatal, counter/compare low data nibble bit name reset r/w description 3 creg[3] 0 w counter data bit 3 2 creg[2] 0 w counter data bit 2 1 creg[1] 0 w counter data bit 1 0 creg[0] 0 w counter data bit 0 3 count[3] 0 r data register bit 3 2 count[2] 0 r data register bit 2 1 count[1] 0 r data register bit 1 0 count[0] 0 r data register bit 0 table 8.7.6 register regcdatam, counter/compare middle data nibble bit name reset r/w description 3 creg[7] 0 w counter data bit 7 2 creg[6] 0 w counter data bit 6 1 creg[5] 0 w counter data bit 5 0 creg[4] 0 w counter data bit 4 3 shcount[7] 0 r data register bit 7 2 shcount[6] 0 r data register bit 6 1 shcount[5] 0 r data register bit 5 0 shcount[4] 0 r data register bit 4 table 8.7.7 register regcdatah, counter/compare high data nibble bit name reset r/w description 3 bitsel[1] 0 r/w bit select for limited bit count/compare 2 bitsel[0] 0 r/w bit select for limited bit count/compare 1 creg[9] 0 w counter data bit 9 0 creg[8] 0 w counter data bit 8 1 shcount[9] 0 r data register bit 9 0 shcount[8] 0 r data register bit 8 table 8.7.8 counter length selection bitsel[1] bitsel[0 ] counter length 0 0 10-bit 018-bit 106-bit 114-bit
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 38 9 millisecond counter the em6521 has a built-in millisecond binary coded decimal counter. it can be used to measure the time elapsed between two events (hardware or software events). with a system clock of 32khz, the counter generates every 1/10 second or every second an interrupt request. the counter value read on registers regmscdatal , regmscdatam and regmscdatah is in binary coded decimal format (000 to 999). to maintain the data integrity for the 3 decimal digits inside bcd[11:0] one must stop the counter while reading the full 3 digit value. an overflow flag flsec is set whenever the counter reached 999. this flag is helpful when the counter is used in polling mode and twice the same value is read. in this case, if the flag is set to 1, it indicates that the two readings were 1 second apart, in the case the flag is not set, the two readings must have been very short one after the other. after every read of regmsccntl2 the flsec gets automatically reset. the millisecond counter is reset with every system reset. setting the resmsc flag located in register regmsccntl1 resets the counter value only. this flag is automatically reset after the write operation. for good resolution in pa3-mode use the ck[14 ] debouncer clock (250us). or if the 1/1000 sec is not relevant then choose ck[10] (4ms) as debouncer clock. doing so will save power. the debouncer selection is made in register regmsccntl2 bit debfreqsel. changing pa3edge while runen =1 or pa3/up =1 may generate a msc event (start or stop). this behavior is useful for the - cpu controlled start and pa3 controlled stop - mode, but in general one does all the setup before starting the counter. 9.1 pa[3] input for msc in hardware start/stop mode the counter is triggered with the port a terminal pa[3] input. in this case pa[3] is debounced with the prescaler ck[14] (or ck[10]) clock. the triggering edge selection is made with bit pa3edge in register regmsccntl2 (default negative edge). the pa[3] input for the millisecond counter is totally independent of the pa[3] interrupt edge selection and the pa[3] polarity selection for the 10 bit counter. however the pull-up or pull-down selection is common to all peripheries sharing the port a. 9.2 irq from msc an interrupt request irqmsc is send on either every 1/10 seconds or every second, depending on the bit intsel in register regmsccntl2 . for interrupt handling please refer to the interrupt control section. figure 27. msc block diagram regmsccntl1,2 pa3 debouncer en irqmsc runen pa3/up dt/msc data bus data data data intsel 1 sec 1/10 sec ck[10] ck[14 pa[3] terminal pa3internal negedg posedg 1 0 pa3edge 0 1 0 1 4 ck1000 flsecl debfreqsel start/stop control dt/msc bcd 1/1000 sec bcd 1/100 sec bcd 1/10 sec this signal used as reference in text description
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 39 9.3 msc-modes the millisecond counter can have many different modes of operation. the most common are : - cpu controlled start and stop. - cpu controlled start and pa[3] controlled stop. - port a terminal pa[3] controlled start and stop mode. - pulse width measurement of port a terminal pa[3] input signals. all these different modes are controlled with the bits in the registers regmsccntl1 and regmsccntl2. the main bits are : - dt/msc ; pulse-width or start stop measure. this bit only has a action if pa[3] input is chosen. if pulse- width measure is selected, the counter starts with the first active edge on pa[3] and stops with the next inverse edge (sets runen = 0). if msc measure selected, the counter starts with the first active pa[3] edge, stops on the next, restarts on the following etc. it does not reset runen . - pa3/p ; direct port a terminal pa[3] or cpu (p) controlled start and stop function. if direct pa[3] controlled start stop mode is chosen the counter, once enabled by setting runen/stop = 1, starts counting on the first active edge seen on pa[3]. it stops counting depending on the dt/msc bit either on the next inverse edge or on the next active edge. if p is chosen, the counter starts and stops depending on bit runen/stop . - runen/stop ; in cpu mode this bit starts or stops the counter. in pa3 mode it enables the counter which will start with the next event on port a terminal pa[3]. if dt and pa3 mode, the runen gets reset with the second active pa[3] edge. - pa3edge ; this bit selects the active pa[3] edge which will trigger the dt/msc selected measurement mode. it has no effect if pa3/p =0. default 0 is negative edge. 9.4 mode selection before using, the msc counter needs to be reset by setting bit resmsc to 1. this bit is automatically reset thereafter. then select the irq frequency and the counting mode. now the runen can be set to 1 . to display the counter value during run you may only want to read the msb (1/10 sec) digit ,driven by irq or with polling, and fully read the msc value only once the counter is stopped. the counter data registers are read only. any reset (system reset, por, watchdog) is setting the msc into stop mode and clears the counter registers. cpu controlled start and stop as soon as the cpu writes the start bit runen/stop =1 the counter starts up counting until the cpu clears the start bit. the bit pa3/up is 0 for this mode. figure 28. cpu controlled start stop counting stop start counter runen/stop cpu write
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 40 cpu controlled start and pa[3] controlled stop. in this mode setting the bit runen =1 while pa3/up =0 while immediately start the counting action. afterwards one needs to prepare for the stop by pa[3]. therefore the pa[3] start condition must first be fulfilled. this is in dt mode a rising edge on the pa3internal signal (pa3internal, refer to figure 27). in msc mode the start condition is a positive pulse on pa3internal signal. the creation of this edge or pulse is done per software by manipulating the pa3edge selection. see figure 29 for details. afterwards one can change to pa3 controlled stop mode ( pa3/up =1) where the next positive edge on pa3internal will stop the counter. in dt mode the runen/stop bit will be cleared with the pa3 stop condition where as in msc mode msc mode the runen is not cleared. pulse-width measurement of pa[3] input signals. in this mode the bit dt/msc =1 and pa3/up =1. setting runen/stop=1 enables the operation. the first positive edge on pa3internal signal will start the counter, the following negative edge will stop the counter end set bit runen/stop to 0 . pa3internal signal is a copy of the pa[3] terminal status if pa3edge =1. with pa3edge =0 pa3internal has the inverted pa[3] value. see also figure 27 and figure 30. port a pa[3] controlled start and stop mode. in this mode the bit dt/msc =0 and pa3/up =1. setting runen/stop=1 enables the operation. the first positive edge on pa3internal signal will start the counter , the second edge will stop the counter, the third one will restart, etc, . pa3internal signal is a copy of the pa[3] terminal status if pa3edge =1. with pa3edge =0 pa3internal has the inverted pa[3] value. see also figure 27 and figure 30. figure 29. cpu controlled start pa[3] controlled stop counting set in itia l values stop start pa3 start p dt/m sc=1, stop on pa[3] risin g ed g e cpu w rite pa3ed g e pa3/up r unen/stop p a 3 in te rn a l c ount pa[3] set in itia l values counting stop start pa3 start p dt/m sc=1, stop on pa[3] fallin g ed g e cpu w rite pa3ed g e pa3/up runen/stop pa3internal count pa[3] counting set in itia l values stop start pa3 start p dt/m sc=0, stop on pa[3] risin g ed g e cpu w rite pa3ed g e pa3/up r unen/stop p a 3 in te rn a l c ount pa[3] counting set in itia l values stop start pa3 start p dt/m sc=0, stop on pa[3] fallin g ed g e cpu w rite pa3ed g e pa3/up runen/stop pa3internal count pa[3] figure 30. dt/msc behavior restart stop start stop start counter runen counting counting counting pa3 internal period measurement dt/msc=0, pa3/up=1 pulse-width measurement dt/msc, pa3/up=1 counter runen pa3 internal
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 41 9.5 millisecond counter registers table 9.5.1 register regmsccntl1 bit name reset r/w description 3 runen/stop 0 r/w enable counter 2 pa3/p 0 r/w port a or cpu start stop control 1 dt/msc 0 r/w pulse-width measurement 0 resmsc 0 r/w reset if write of 1 read value is always 0 default: stop, cpu controlled. table 9.5.2 register regmsccntl2 bit name reset r/w description 3 debfreqsel 0 r/w debouncer frequency select 2 pa3edge 0 r/w pa[3] edge selection 1 intsel 0 r/w interrupt source selection 0 flsec 0 r seconds flag default: ck[14] is debouncer clock, negative edge, 1/10 sec interrupt requests table 9.5.3 register regmscdatal bit name reset r/w description 3 bcd[3] 0 r 1/1000 seconds bcd value 3 2 bcd[2] 0 r 1/1000 seconds bcd value 2 1 bcd[1] 0 r 1/1000 seconds bcd value 1 0 bcd[0] 0 r 1/1000 seconds bcd value 0 table 9.5.4 register regmscdatam bit name reset r/w description 3 bcd[7] 0 r 1/100 seconds bcd value 3 2 bcd[6] 0 r 1/100 seconds bcd value 2 1 bcd[5] 0 r 1/100 seconds bcd value 1 0 bcd[4] 0 r 1/100 seconds bcd value 0 table 9.5.5 register regmscdatah bit name reset r/w description 3 bcd[11] 0 r 1/10 seconds bcd value 3 2 bcd[10] 0 r 1/10 seconds bcd value 2 1 bcd[9] 0 r 1/10 seconds bcd value 1 0 bcd[8] 0 r 1/10 seconds bcd value 0
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 42 10 interrupt controller the em6521 has 12 different interrupt request sources, each of which is maskable. five of them come from external sources and seven from internal sources. external(4) - port a, pa[3] .. pa[0] inputs - serial interface internal(8) - prescaler ck[1], blink, 32hz/8hz - melody timer - serial interface - millisecond-counter 1/10sec or 1sec - 10-bit counter count0, countcomp to be able to send an interrupt to the cpu, at least one of the interrupt request flags must 1 ( irqxx ) and the general interrupt enable bit inten located in the register regsyscntl1 must be set to 1. the interrupt request flags can only be set high by a positive edge on the irqxx data flip-flop while the corresponding mask register bit ( maskirqxx ) is set to 1. at power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any interrupt request to be stored. also the general interrupt enable inten is set to 0 (no irq to cpu) by reset. after each read operation on the interrupt request registers regirq1 , regirq2 or regirq3 the contents of the addressed register are reset. therefore one has to make a copy of the interrupt request register if there was more than one interrupt to treat. each interrupt request flag may also be reset individually by writing 1 into it . interrupt handling priority must be resolved through software by deciding which register and which flag inside the register need to be serviced first. since the cpu has only one interrupt subroutine and the irqxx registers are cleared after reading, the cpu does not miss any interrupt request which comes during the interrupt service routine. if any occurs during this time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine. figure 31. interrupt controller block diagram interrupt request capture re g ister 12 input-or read clrintbit reset general int en irq to p one of these blocks for each irq db db[n] irqxx write mask write
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 43 any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the interrupt request register. all interrupt requests are stored in their irqxx registers depending only on their mask setting and not on the general interrupt enable status. whenever the em6521 goes into halt mode the inten bit is automatically set to 1, thus allowing to resume from halt mode with an interrupt. 10.1 interrupt control registers table 10.1.6 register regirq1 bit name reset r/w description 3 irqpa[3] 0 r * port a pa[3] interrupt request 2 irqpa[2] 0 r * port a pa[2] interrupt request 1 irqpa[1] 0 r * port a pa[1] interrupt request 0 irqpa[0] 0 r * port a pa[0] interrupt request *; writing of 1 clears the corresponding bit. table 10.1.7 register regirq2 bit name reset r/w description 3 irqhz1 0 r * prescaler interrupt request 2 irqhz32/8 0 r * prescaler interrupt request 1 irqblink 0 r * prescaler interrupt request 0 irqbz 0 r * melody timer interrupt request *; writing of 1 clears the corresponding bit. table 10.1.8 register regirq3 bit name reset r/w description 3 irqserial 0 r * serial interrupt request 2 irqmsc 0 r * millisecond counter int. request 1 irqcount0 0 r * counter interrupt request 0 irqcntcomp 0 r * counter interrupt request *; writing of 1 clears the corresponding bit. table 10.1.9 register regirqmask1 bit name reset r/w description 3 maskirqpa[3] 0 r/w port a pa[3] interrupt mask 2 maskirqpa[2] 0 r/w port a pa[2] interrupt mask 1 maskirqpa[1] 0 r/w port a pa[1] interrupt mask 0 maskirqpa[0] 0 r/w port a pa[0] interrupt mask interrupt is not stored if the mask bit is 0. table 10.1.10 register regirqmask2 bit name reset r/w description 3 maskirqhz1 0 r/w prescaler interrupt mask 2 maskirqhz32/8 0 r/w prescaler interrupt mask 1 maskirqblink 0 r/w prescaler interrupt mask 0 maskirqbz 0 r/w melody timer interrupt mask interrupt is not stored if the mask bit is 0. table 10.1.11 register regirqmask3 bit name reset r/w description 3 maskirqserial 0 r/w serial interrupt mask 2 maskirqmsc 0 r/w millisecond counter int. mask 1 maskirqcount0 0 r/w counter interrupt mask 0 maskirqcntcomp 0 r/w counter interrupt mask interrupt is not stored if the mask bit is 0
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 44 11 supply voltage level detector the em6521 has a built-in supply voltage level detector (svld) circuitry, such that the cpu can compare the supply voltage against a pre-selected value. during sleep mode this function is inhibited. the cpu activates the supply voltage level detector by writing vldstart = 1 in the register regvldcntl . the actual measurement starts on the next ck[9] rising edge and lasts during the ck[9] high period (2 ms at 32 khz). the busy flag vldbusy stays high from vldstart set until the measurement is finished. the worst case time until the result is available is 1.5 ck[9] prescaler clock periods (32 khz -> 6 ms). the detection level must be defined in register regvldlevel before the vldstart bit is set. during the actual measurement (2 ms) the device will draw an additional 5 a of i vdd current. after the end of the measure the result is available by inspection of the bit vldresult . if the result is read 0, then the power supply voltage was greater than the detection level value. if read 1, the power supply voltage was lower than the detection level value. during each read while busy=1 the vldresult is not guaranteed. for compatibility reasons the svld levels available on the em6521 are kept the same as the levels used on the em6621. this means that all levels which may be lower2.0v could not be reached anymore because they are below vddmin. 11.1 svld register table 11.1.1 register regvldcntl bit name reset r/w description 3 vldresult 0 r* vld result flag 2 vldstart 0 w vld start 2 vldbusy 0 r vld busy flag 1 nooscwd 0 r/w no oscillator watchdog 0 nologicwd 0 r/w no logic watchdog r*; read value while vldbusy=1 is not guaranteed. table 11.1.2 register regvldlevel (detection level value) bit name reset r/w description 3 -- x -- not active 2 vldlevel2 0 r/w vld level selection 1 vldlevel1 0 r/w vld level selection 0 vldlevel0 0 r/w vld level selection table 11.1.3 voltage level detector value selecting vldlevel2 vldlevel1 vldlevel0 typical voltage level level1 0 0 0 4.00 level2 0 0 1 2.95 level3 0 1 0 2.35 level4 0 1 1 1.95*1 level5 1 0 0 1.70**2 level6 1 0 1 1.45**2 level7 1 1 0 1.30**2 level8 1 1 1 1,20**2 *1 level which may not be reached anymore because it can be lower than vddmin. **2 levels which are too far below vddmin to be reached. (are here for software compatibility with em6621). figure 32. svld timing diagram vbat =v dd compare level ck[9] (256 hz) cpu starts measure busy flag measure 1 0 result read result svld > vbat svld < vbat cpu starts measure
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 45 12 strobe output the strobe output is used to indicate either the em6521 reset condition, a write operation on port b (writepb) or the sleep mode. the selection is done in register reglcdcntl1 . per default, the reset condition is output on the strobe terminal. for a port b write operation the strobe signal goes high for half a system clock period. data can be latched on the falling edge of the strobe signal. this function is used to indicate when data on port b output terminals is changing. the reset signal on the strobe output is a copy of the internal cpu reset signal. the strobe pin remains active high as long as the cpu gets the reset. both the reset condition and the port b write operation can be output simultaneously on the strobe pin. the strobe output select latches are reset by initial power on reset only. table 11.1.1. strobe output selection strobeoutsel1 strobeoutsel0 strobe terminal output 00system reset 01 system reset and writepb 10writepb 1 1 sleep 12.1 strobe register table 12.1.1 register reglcdcntl1 bit name power on value r/w description 3 strobeoutsel1 0 r/w strobe output select 2 strobeoutsel0 0 r/w strobe output select 1 cktripsel1 0 r/w lcd multiplier clock select 0 cktripsel0 0 r/w lcd multiplier clock select the cktripsel1, cktripsel0 values are reset with every system reset. figure 33 . strobe output reset, writepb strobeoutsel1 strobeoutsel0 sleep writepb reset 3 01 2 1 0 terminal strobe
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 46 13 ram the em6521 has two 64x4 bit rams built-in. the main ram (ram1) is direct addressable on addresses decimal(0 to 63). a second ram (ram2) is indirect addressable on addresses 64,65, 66 and 67 together with the index from regindexadr. the ram2 addressing is indirect using the regindexadr value as an offset to the directly addressed base ram2_0 , ram2_1 , ram2_2 or ram2_3 registers. to write or read the ram2 the user has first to set the offset value in the regindexadr register. the actual access then is made on the ram2 base addresses ram2_0 , ram2_1, ram2_2 or ram2_3. refer to figure 34. ram architecture, for the address mapping. i.e. writing hex(5) to ram2 add location 30: first write hex(e) to regindexadr, then write hex(5) to ram2_1 ram extension : unused r/w registers can often be used as possible ram extension. be careful not to use register which start, stop, or reset some functions. unused lcd register latches can also be used as ram memory. in case of 3 times multiplex and using all the 20 segment outputs you may have five additional 4 bit registers.. also for each unused segment output you may have one additional 4 bit register. figure 34. ram architecture ram1_63 ram1_62 ram1_61 ram1_60 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] ram1_0 4 bit r/w 4 bit r/w 4 bit r/w 4 bit r/w 4 bit r/w . . . . . . ram1_3 ram1_2 ram1_1 ram2_3 ram2_2 ram2_1 4 bit r/w ram2_0 4 bit r/w 4 bit r/w 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 64 x 4 indexed addressable ram2 64 x 4 direct addressable ram1
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 47 14 lcd driver the em6521 has a built-in liquid crystal display (lcd) driver. a maximum of 80 segments can be displayed using the 20 segment driver outputs (seg[20:1) in 4:1 multiplex ,60 segments in the case of 3:1 multiplex, and the 4 back-planes (com[4:1]). the lcd driver has its own voltage regulator (1.05 volt) and voltage multiplier to generate the driver bias voltages vl1, vl2 and vl3 (vlcd). using the metal1 mask (rom version only) the user can choose higher lcd reference voltages. please check with em marin the possible values and their impact on power consumption. the special architecture of this lcd driver allows the user to freely specify the data and address for each individual segment using the interconnect metal2 mask (rom version only) . it therefore adapts to every possible lcd display with a maximum of 80 independent segments. the lcd clock frequency is 256hz. thus the frame frequency is 256/8 hz if 4:1 multiplex, or 256/6 if 3:1 multiplex. figure 35. lcd architecture reflcd lcd external supply lcd blank address bus seg[n] x3 enable x2 x1 voff lcd off von mux output switches voltage multiplier phase selection data latches data bus phase 1 to 4 3 4 2 1 vl1 vl2 vl3
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 48 14.1 lcd control the lcd driver has two control registers reglcdcntl1 , reglcdcntl2 to optimize for display contrast, power consumption, operation mode and bias voltage source. lcdextsupply: choosing external supply ( lcdextsupply =1) disables the internal lcd voltage regulator and voltage multiplier, it also puts the bias voltage terminals vl1, vl2 and vl3 into high impedance state. external bias levels can now be connected to vl1, vl2 and vl3 terminals. (resistor divider chain or others). another way to adapt the vl1, vl2 and vl3 levels to specific user needs is to overdrive the vl1 output (lcdextsupply =0) with the desired value. the internal multiplier will multiply this new vl1 level to generate the corresponding levels vl2 and vl3. the bit lcdextsupply is only reset by initial por. lcd4mux: with this switch one selects either 3:1 or 4:1 (default) times multiplexing of the 20 segment driver outputs. in the case of 3:1 multiplexing the com[4] is off. lcdoff: disables the lcd. the voltage multiplier and regulator are switched off ( 0 current ).the segment latch information is maintained. the vl1,vl2 and vl3 outputs are pulled to v ss . lcdblank: all segment outputs are turned off. the voltage multiplier and regulator remain switched on. lcdblank can be used with the 1hz and blink interrupt to let the whole display blink (software controlled). cktripsel1,0: selecting the appropriate voltage multiplier frequency to optimize display contrast and power consumption. the value to use is also depending on the selected multiplier booster capacitors (typically 100nf). 14.2 lcd addressing the lcd driver addressing is indirect using the regindexadr value as an offset to the directly addressed base lcd_1 , lcd_2 or lcd_3 registers. all lcd segment registers are r/w. at address lcd_3 only the first 8 index locations are usable. the index locations hex(8 to f) are non implemented. a total of 40 addresses are available to the user to freely define the addressing of the lcd segment latches. for each of these latches the user may choose the address and data to be connected. see also section 14.3. however only 20x4 lcd segment latches are implemented. the unused address locations are empty and can not be used as ram. figure 36. lcd address mapping lcd_3 lcd_2 lcd_1 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 4 bit r/w regindexadr[8] regindexadr[7] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 40 x 4 indexed addressable lcd latches but maximum 20x4 bits are r/w
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 49 14.3 free segment allocation each segment (seg[20:1]) terminal outputs the time multiplexed information from its 4 segment data latches. information stored in latch 1 is output during phase1, latch 2 during phase 2, latch 3 during phase 3 and latch 4 during phase 4. in the case of 3 to 1 multiplexing the phase 4 and the latch 4 are not used. this phase information on the segment outputs together with the common outputs (com[4:1]) - also called back-planes - defines if a given lcd segment is light or not. com[1] is on during phase 1 and off during phase 2,3,4 , com[2] is on during phase 2 and off during phase 1,3,4 , etc. for each segment data latch the address location within the lcd address spacing ( lcd_3 + index(8), lcd_2 + index(16), lcd_1 + index(16) --> lcdadr[39:0] ) can be user defined. for each segment data latch the data bus connection (db[3:0]) can be user defined. table 14.3.1 default lcd configuration used on em6521 segment outputs com[1] = phase1 com[2] = phase2 com[3] = phase3 com[4] = phase4 seg[1] db[0], lcdadr[0] db[1], lcdadr[0] db[2], lcdadr[0] db[3], lcdadr[0] seg[2] db[0], lcdadr[1] db[1], lcdadr[1] db[2], lcdadr[1] db[3], lcdadr[1] seg[3] db[0], lcdadr[2] db[1], lcdadr[2] db[2], lcdadr[2] db[3], lcdadr[2] ... ... ... ... ... seg[18] db[0], lcdadr[18] db[1], lcdadr[18] db[2], lcdadr[18] db[3], lcdadr[18] seg[19] db[0], lcdadr[19] db[1], lcdadr[19] db[2], lcdadr[19] db[3], lcdadr[19] seg[20] db[0], lcdadr[20] db[1], lcdadr[20] db[2], lcdadr[20] db[3], lcdadr[20] 14.4 lcd registers table 14.4.1 register reglcdcntl1 bit name reset r/w description 3 strobeoutsel1 por to 0 r/w strobe output select 2 strobeoutsel0 por to 0 r/w strobe output select 1 cktripsel1 0 r/w lcd multiplier clock select 0 cktripsel0 0 r/w lcd multiplier clock select strobeoutsel1,0 is reset by initial power on only. table 14.4.2 multiplier clock frequency select cktripsel0 cktripsel1 multiplier clock on 32 khz operation 0 0 ck[10] 512 hz 1 0 ck[9] 256 hz 0 1 ck[8] 128 hz 1 1 ck[7] 64 hz table 14.4.3 register lcdcntl2 bit name reset r/w description 3 lcdblank 1 r/w lcd segment outputs off 2 lcdoff 1 r/w lcd off (multiplier off) 1 lcd4mux 1 r/w 4 : 1 multiplexed 0 lcdextsupply por to 0 r/w external supply for vl1, vl2 and vl3 lcdextsupply is reset to 0 by por only.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 50 figure 37 lcd multiplexing waveform value = hex 8 seg[5] vl1 vl2 vl3 v ss com2 com1 vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss frame cklcd com4 com3 vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss seg[4] seg[3] vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss value = hex 4 value = hex 2 seg[2] seg[1] vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss value = hex 1 value = hex 0 com4 - seg[5] vl1 vl2 vl3 v ss value = hex 8 -vl2 -vl1 -vl3 com3 - seg[4] vl1 vl2 vl3 v ss value = hex 4 -vl2 -vl1 -vl3 com2 - seg[3 ] vl1 vl2 vl3 v ss value = hex 2 -vl2 -vl1 -vl3 com1 - seg[1 ] vl1 vl2 vl3 v ss value = hex 0 -vl2 -vl1 -vl3 com1 - seg[2 ] vl1 vl2 vl3 v ss value = hex 1 -vl2 -vl1 -vl3 seg[2] seg[1] com3 com4 seg[5] seg[4] seg[3] com1 com2
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 51 15 peripheral memory map reset values are valid after power up or after every system reset. register name add hex add dec. reset value read bits write bits remarks b'3210 read / write bits ram1_0 00 0 xxxx 0: data0 1: data1 2: data2 3: data3 normal addressable ram 64x4 bit ... ... ... ... ... ram1_63 3f 63 xxxx 0: data0 1: data1 2: data2 3: data3 normal addressable ram 64x4 bit ram2_0 40 64 xxxx 0: data0 1: data1 2: data2 3: data3 16 nibbles addressable over index register on add 'h70 ... ... ... ... ram2_3 43 67 xxxx 0: data0 1: data1 2: data2 3: data3 16 nibbles addressable over index register on add 'h70 lcd_1 44 68 xxxx connections are user definable. see lcd section 16 nibbles addressable over index register on add 'h70 lcd_2 45 69 xxxx connections are user definable. see lcd section 16 nibbles addressable over index register on add 'h70 lcd_3 46 70 xxxx connections are user definable. see lcd section the 8 lower nibbles are addressable over the index register on add 'h70. the 8 higher nibbles are not used and not implemented --- 47 71 reserved, not implemented ... ... ... ... --- 4f 79 reserved, not implemented regpa 50 80 xxxx 0: padata[0] 1: padata[1] 2: padata[2] 3: padata[3] ---- read port a directly regpbcntl 51 81 0000 0: pbiocntl[0] 1: pbiocntl[1] 2: pbiocntl[2] 3: pbiocntl[3] port b control default: input mode
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 52 register name add hex add dec. reset value read bits write bits remarks b'3210 read / write bits regpbdata 52 82 0000 0: pb[0] 1: pb[1] 2: pb[2] 3: pb[3] 0: pbdata[0] 1: pbdata[1] 2: pbdata[2] 3: pbdata[3] port b data output pin port b read default : 0 regscntl1 53 83 0000 0: msbnlsb 1: posnneg 2: ms0 3: ms1 serial interface control 1 regscntl2 54 84 0000 0: om[0] 1: om[1] 2: status 3: start serial interface control 2 regsdatal 55 85 0000 0: serdatal[0] 1: serdatal[1] 2: serdatal[2] 3: serdatal[3] serial interface low data nibble regsdatah 56 86 0000 0: serdatah[0] 1: serdatah[1] 2: serdatah[2] 3: serdatah[3] serial interface high data nibble regspdata 57 87 0000 0: psp[0] 1: psp[1] 2: psp[2] 3: psp[3] 0: serpdata[0] 1: serpdata[1] 2: serpdata[2] 3: serpdata[3] serial interface parallel data out regmelfsel 58 88 0000 0: melfsel[0] 1: melfsel[1] 2: melfsel[2] 3: bzouten melody frequency select and output enable control regmeltim 59 89 0000 0:ftimsel0 1:ftimsel1 2:auto 3:flbuzzer 0:ftimsel0 1:ftimsel1 2:auto 3:swbuzzer melody timer control regmelperi 5a 90 0000 0: - 1: - 2: - 3: - 0: per[0] 1: per[1] 2: per[2] 3: per[3] melody timer period regccntl1 5b 91 0000 0: countfsel0 1: countfsel1 2: countfsel2 3: up/down 10-bit counter control 1; frequency and up/down regccntl2 5c 92 0000 0: '0' 1: encomp 2: evcount 3: start 0 : load 1: encomp 2: evcount 3: start 10-bit counter control 2; comparison, event counter and start regcdatal 5d 93 0000 0: count[0] 1: count[1] 2: count[2] 3: count[3] 0: creg[0] 1: creg[1] 2: creg[2] 3: creg[3] 10-bit counter data low nibble regcdatam 5e 94 0000 0: count[4] 1: count[5] 2: count[6] 3: count[7] 0: creg[4] 1: creg[5] 2: creg[6] 3: creg[7] 10-bit counter data middle nibble regcdatah 5f 95 0000 0: count[8] 1: count[9] 2: bitsel[0] 3: bitsel[1] 0: creg[8] 1: creg[9] 2: bitsel[0] 3: bitsel[1] 10 bit counter data high bits
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 53 register name add hex add dec. reset value read bits write bits remarks b'3210 read / write bits regmsccntl1 60 96 0000 0: '0' 1: dt/msc 2: pa3/p 3:runen/stop 0: resmsc 1: dt/msc 2: pa3/p 3:runen/stop millisecond counter control register 1; reset, delta time, control source regmsccntl2 61 97 0000 0: flsec 1: intsel 2: pa3edge 3: debfreqsel 0: -- 1: intsel 2: pa3edge 3: debfreqsel millisecond counter control register 2; 1 sec flag, interrupt and pa3 edge select regmscdatal 62 98 0000 0: bcd[0] 1: bcd[1] 2: bcd[2] 3: bcd[3] 0: - 1: - 2: - 3: - millisecond counter; binary coded decimal value, low nibble regmscdatam 63 99 0000 0: bcd[4] 1: bcd[5] 2: bcd[6] 3: bcd[7] 0: - 1: - 2: - 3: - millisecond counter; binary coded decimal value, middle nibble regmscdatah 64 100 0000 0: bcd[8] 1: bcd[9] 2: bcd[10] 3: bcd[11] 0: - 1: - 2: - 3: - millisecond counter; binary coded decimal value, high nibble regirqmask1 65 101 0000 0: maskirqpa[0] 1: maskirqpa[1] 2: maskirqpa[2] 3: maskirqpa[3] port a interrupt mask; masking active 0 regirqmask2 66 102 0000 0: maskirqbz 1: maskirqblink 2: maskirqhz32/8 3: maskirqhz1 buzzer and prescaler interrupt mask; masking active low regirqmask3 67 103 0000 0: maskirqcntcomp 1: maskirqcount0 2: maskirqmsc 3: maskirqserial 10-bit counter, millisecond counter, serial interrupt mask masking active low regirq1 68 104 0000 0: irqpa[0] 1: irqpa[1] 2: irqpa[2] 3:irqpa[3] 0:rirqpa[0] 1:rirqpa[1] 2:rirqpa[2] 3:rirqpa[3] read: port a interrupt write: reset irq if data bit = 1. regirq2 69 105 0000 0: irqbz 1: irqblink 2: irqhz32/8 3: irqhz1 0:rirqbz 1:rirqblink 2:rirqhz32/8 3:rirqhz1 read: buzzer and prescaler irq ; write: reset irq id data bit = 1 regirq3 6a 106 0000 0:irqcntcomp 1: irqcount0 2: irqmsc 3: irqserial 0:rirqcntcomp 1:rirqcount0 2:rirqmsc 3:rirqserial read: 10-bit counter, millisecond counter, serial interrupt write: reset irq if data bit =1. regsyscntl1 6b 107 0000 0: chtmdis 1: selintfull 2: '0' 3: inten 0: chtmdis 1: selintfull 2: sleep 3: inten system control 1 chtmdis only usable only for em test modes with test=1 regsyscntl2 6c 108 0p00 p = por 0: wdval0 1: wdval1 2: sleepen 3: '0' 0: -- 1: -- 2: sleepen 3: wdreset system control 2; watchdog value and periodical reset, enable sleep mode
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 54 register name add hex add dec. reset value read bits write bits remarks b'3210 read / write bits regpresc 6d 109 0000 0: debsel 1: printsel 2: '0' 3: pwmon 0: debsel 1: printsel 2: respresc 3: pwmon prescaler control; debouncer and prescaler interrupt select ixlow 6e 110 xxxx 0: ixlow[0] 1: ixlow[1] 2: ixlow[2] 3: ixlow[3] internal p index register low nibble; for p indexed addressing ixhigh 6f 111 xxxx 0: ixhigh[4] 1: ixhigh[5] 2: ixhigh[6] 3: '0' 0: ixhigh[4] 1: ixhigh[5] 2: ixhigh[6] 3: -- internal p index register high nibble; for p indexed addressing regindexadr 70 112 0000 0: indexadr[0] 1: indexadr[1] 2: indexadr[2] 3: indexadr[3] indexed addressing register for 4x16 nibble ram2 and 3x16 + 8 nibble lcd reglcdcntl1 71 113 pp00 0: cktripsel0 1: cktripsel1 2: strobeoutsel0 3: strobeoutsel1 lcd control 0; multiplier clock and strobe output select reglcdcntl2 72 114 111p 0: lcdextsupply 1: lcd4xmux 2: lcdoff 3: lcdblank lcd control 1; main selects regvldcntl 73 115 0000 0: nologicwd 1: nooscwd 2: vldbusy 3: vldresult 0: nologicwd 1: nooscwd 2: vldstart 3: -- voltage level detector control regvldlevel 74 116 x000 0: vldlevel0 1: vldlevel1 2: vldlevel2 3: -- voltage level detector; detection level selection p = defined by por (power on reset)
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 55 16 option register memory map the values of the option registers are set by initial reset on power up and through write operations only. other resets ; as reset from watchdog, reset from input port a, reset from pin reset, etc. do not change the options register value . register name add hex add dec. reset value read bits write bits remarks b'3210 read / write bits optdebintpa opt[3:0] 75 117 0000 0: nodebintpa[0] 1: nodebintpa[1] 2: nodebintpa[2] 3: nodebintpa[3] debouncer on port a for interrupt gen. default: debouncer on optintedgpa opt[7:4] 76 118 0000 0: intedgpa[0] 1: intedgpa[1] 2: intedgpa[2] 3: intedgpa[3] interrupt edge select on port a. default: pos. edge optnopullpa opt[11:8] 77 119 0000 0: nopullpa[0] 1: nopullpa[1] 2: nopullpa[2] 3: nopullpa[3] pull-down selection on port a default: pull-down optnopdpb opt[15:12] 78 120 0000 0: nopdpb[0] 1: nopdpb[1] 2: nopdpb[2] 3: nopdpb[3] pull-down selection on port b default: pull-down optnchopdpb opt[19:16] 79 121 0000 0: nchopdpb[0] 1: nchopdpb[1] 2: nchopdpb[2] 3: nchopdpb[3] nch. open drain output on port b default: cmos output optnchopdps opt[23:20] 7a 122 0000 0: nchopdps[0] 1: nchopdps[1] 2: nchopdps[2] 3: nchopdps[3] nch. open drain output on port serial default: cmos output optfselpb opt[31:28] 7b 123 0000 0: pb1hzout 1: pb1khzout 2: pb32khzout 3: inpressleep frequency output on port b, reset from sleep mode with port a optinprsel1 7c 124 0000 0: inpres1pa[0] 1: inpres1pa[1] 2: inpres1pa[2] 3: inpres1pa[3] reset through port a inputs selection. refer to reset part optinprsel2 7d 125 0000 0: inpres2pa[0] 1: inpres2pa[1] 2: inpres2pa[2] 3: inpres2pa[3] reset through port a inputs selection. refer to reset part optnopdps opt[35:32] 7e 126 0000 0: nopdps[0] 1: nopdps[1] 2: nopdps[2] 3: nopdps[3] no pull-down on port sp default: pull-down regtestem 7f 127 ---- ---- ---- for em test only;
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 56 17 active supply current test the same test loop as in the rom version is used. the introduction of this test loop limits the maximum user allowable instructions in the rom version to 4091 words. in the em6521 however the user has full use of all the 4096 implemented words. testloop : ;reset watchdog here sti 00h, 05h ;test loop sti 75h 0ah ldr 00a ldr 75h jmp testloop
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 57 18 mask options most options which in many controllers are realized as metal mask options are directly user selectable with the option registers, therefore allowing a maximum freedom of choice .see chapter: option register memory map. the following options can be selected at the time of programming the metal mask rom, except the lcd segment allocation which is defined using the interconnect metal2 mask. the em6521 is delivered with the default metal mask settings. if you need other mask settings please contact em microelectronic marin sa 18.1 input / output ports 18.1.1 port a metal options (for rom version) pull-up or no pull- up can be selected for each port a input. a pull-up selection is excluding a pull-down on the same input. pull-down (default) or no pull-down can be selected for each port a input. a pull-down selection is excluding a pull-up on the same input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. the default resistor r1 value is 100 kohm. to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : no pull-up figure 38. port a pull options resistor r1 mpapdstrong[n] strong pull-down mpapustrong[n] strong pull-up pull-up control pa[n] terminal 100 kohm no pull-up no pull-down pull-down control or input circuitry vbat option name strong pull- down r1 value typ.100 k no pull- down 1 3 4 mpapd[3] pa3 input pull-down x 100k mpapd[2] pa2 input pull-down x 100k mpapd[1] pa1 input pull-down x 100k mpapd[0] pa0 input pull-down x 100k option name strong pull-up r1 value typ.100k no pull-up 1 3 4 mpapu[3] pa3 input pull-up 100k x mpapu[2] pa2 input pull-up 100k x mpapu[1] pa1 input pull-up 100k x mpapu[0] pa0 input pull-up 100k x
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 58 18.1.2 port b metal options (for rom version) pull-up or no pull-up can be selected for each port b input. the pull-up is only active in nch. open drain mode. pull-down or no pull-down can be selected for each port b input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. the default resistor r1 value is 100 kohm. to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-up with r1=100 kohm figure 39. port b pull options resistor r1 mpbpdstrong[n] strong pull-down mpbpustrong[n] strong pull-up pull-up control pb[n] terminal 100 kohm no pull-up no pull-down pull-down control or input circuitry vbat option name strong pull- down r1 value typ.100k no pull- down 1 3 4 mpbpd[3] pb3 input pull-down x 100k mpbpd[2] pb2 input pull-down x 100k mpbpd[1] pb1 input pull-down x 100k mpbpd[0] pb0 input pull-down x 100k option name strong pull-up r1 value typ. 100k no pull-up 1 3 4 mpbpu[3] pb3 input pull-up x 100k mpbpu[2] pb2 input pull-up x 100k mpbpu[1] pb1 input pull-up x 100k mpbpu[0] pb0 input pull-up x 100k
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 59 18.1.3 port sp metal options (for rom version) pull-up or no pull-up can be selected for each port sp input. the pull-up is only active in nch. open drain mode. pull-down or no pull-down can be selected for each port sp input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. the default resistor r1 value is 100 kohm. to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-up with r1=100 kohm 18.1.4 voltage regulator option (for rom version) by default the internal voltage regulator supplies the core logic the ram and the rom. with option mvreg(a) the regulator is cut and vbat is supplying the core logic the rom and the ram. figure 40. port sp pull options resistor r1 mpspdstrong[n] strong pull-down mpspustrong[n] strong pull-up pull-up control psp[n] terminal 100 kohm no pull-up no pull-down pull-down control or input circuitry vbat option name strong pull- down r1 value typ.100k no pull- down 1 3 4 mpspd[3] pb3 input pull-down x 100k mpspd[2] pb2 input pull-down x 100k mpspd[1] pb1 input pull-down x 100k mpspd[0] pb0 input pull-down x 100k option name strong pull-up r1 value typ. 100k no pull-up 1 3 4 mpspu[3] pb3 input pull-up x 100k mpspu[2] pb2 input pull-up x 100k mpbpu[1] pb1 input pull-up x 100k mpspu[0] pb0 input pull-up x 100k option name default value user value a b mvreg voltage regulator yes
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 60 18.1.5 debouncer frequency option (rom version only) by default the debouncer frequency is ck[11]. the user may choose ck[14] instead of ck[11]. ck[14 ]corresponds to maximum 0.25ms debouncer time in case of a 32khz oscillator. 18.1.6 user defined lcd segment allocation (for rom version) if using a different segment allocation from the one described in chapter 14.3 , one needs to fill in following table. the segment allocation connection are realized with the interconnect metal2 mask. 4 times mux com[1] com[2] com[3] com[4] 3 times mux com[1] com[2] com[3] -- seg[1] seg[2] seg[3] seg[4] seg[5] seg[6] seg[7] seg[8] seg[9] seg[10] seg[11] seg[12] seg[13] seg[14] seg[15] seg[16] seg[17] seg[18] seg[19] seg[20] the customer should specify the required options at the time of ordering. a copy of the pages 57 to 60, as well as the ? software rom characteristic file ? generated by the assembler (*.sta) should be attached to the order. option name default value user value a b mdeb debouncer freq. ck[11]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 61 19 measured electrical behaviors 19.1 idd current 19.2 regulator voltage 19.3 pull resistors vreg vdd=3.0v 1.6 1.8 2.0 2.2 2.4 -20 0 20 40 60 80 [c] [v] vreg temp = 25c 1.6 1.8 2.0 2.2 1.5 2 2.5 3 3.5 4 vdd [v] vreg load dependency 25c -40c 85c 1.1 1.4 1.7 2 2.3 0 100 200 300 400 500 ua [v] pull-down portb; vdd=3.0v 50.0 75.0 100.0 125.0 150.0 -40-20 0 20406080 [c] [kohm] pull-up portb; vdd=3.0v 50 75 100 125 150 -20 0 20406080 [c] [kohm] i(vdd) cpu in active mode, vdd=3.0v 9.0 10.0 11.0 12.0 13.0 -20 0 20 40 60 80 [c] [ua] i(vdd) sleep mode, vdd = 3.0v 25 50 75 100 125 -20 0 20 40 60 80 [c] [na] i(vdd) lcd off, halt mode, vdd = 3.0v 1700 1800 1900 2000 2100 -20 0 20406080 [c] [ua] i(vdd) cpu in active mode, vdd=5.0v 14.0 15.0 16.0 17.0 18.0 -20 0 20 40 60 80 [c] [ua] i(vdd) sleep mode, vdd =5.0v 25 50 75 100 125 -20 0 20 40 60 80 [c] [na] i(vdd) lcd off, halt mode, vdd = 5.0v 1800 1900 2000 2100 2200 -20 0 20406080 [c] [ua]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 62 19.4 output currents ioh portb; vdd=3.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 -10 -8 -6 -4 -2 0 -20 0 20 40 60 80 [c] [ma] iol portb; vdd=3.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 0 3 6 9 12 15 -20 0 20 40 60 80 [c] [ma] iol portb; vdd=5.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 0 4 8 12 16 20 -20 0 20 40 60 80 [c] [ma] ioh portb; vdd=5.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 -12 -9 -6 -3 0 -20 0 20 40 60 80 [c] [ma] iol portb, vds=0.15v/0.3v/0.5v/1.0v; t=25c 0.15v 0.3v 0.5v 1v 0 4 8 12 16 20 2345 [v] [ma] ioh portb; vds=0.15v/0.3v/0.5v/1v; t=25c 0.15v 0.3v 0.5v 1v -12 -9 -6 -3 0 2345 [v] [ma]
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 63 20 em6521 electrical specification 20.1 absolute maximum ratings min. max. units power supply v dd -v ss - 0.2 + 6.0 v input voltage v ss - 0,2 v dd +0,2 v storage temperature - 40 + 125 c electrostatic discharge to mil-std-883c method 3015.7 with ref. to v ss -2000 +2000 v maximum soldering conditions 10s x 250 c stresses above these listed maximum ratings may cause permanent damage to the device. exposure beyond specified electrical characteristics may affect device reliability or cause malfunction. 20.2 handling procedures this device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other cmos component. unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 20.3 standard operating conditions parameter min typ max unit description temperature 0 25 60 c vdd_range 2 3.0 5.5 v with internal voltage regulator vss 0 v reference terminal c vddca (note 1) 100 nf regulated voltage capacitor fq 32768 hz nominal frequency rqs 35 kohm typical quartz serial resistance cl 8.2 pf typical quartz load capacitance df/f +/- 30 ppm quartz frequency tolerance note 1: this capacitor filters switching noise from vdd to keep it away from the internal logic cells. in noisy systems the capacitor should be chosen bigger than minimum value. 20.4 dc characteristics - power supply conditions: vdd=3.0v, t=25c, unless otherwise specified parameter conditions symb. min. typ. max. unit active supply current (note2,3) iv dda 11 15 $ (in active mode with lcd on) 0 ... 60c (note2,3) iv dda 16 $ standby supply current iv ddh 1.8 3 $ (in halt mode, lcdoff) 0 ... 60c iv ddh 3.5 $ sleep supply current iv dds 0.1 0.3 $ 0 ... 60c iv dds 0.5 $ por static level 0 ... 60c, no load on vreg v por 1.6 2.0 v ram data retention 0 ... 60c v rd 1.6 v regulated voltage halt mode, no load v reg 22.3v note 2: lcd display not connected. note 3: for test reasons, the user has to provide a test loop with successive writing and reading of two different addresses (5 instructions should be reserved for this measurement).
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 64 20.5 supply voltage level detector parameter conditions symbol min. typ. max. unit svld voltage level1 0 ... 60c v svld1 3.65 4.01 4.35 v svld voltage level2 0 ... 60c v svld2 2.70 2.99 3.27 v svld voltage level3 0 ... 60c v svld3 2.20 2.42 2.65 v svld voltage level4 note 4 v svld4 1.82 2.01 2.20 v svld voltage level5 note 5 v svld5 1.62 1.77 1.93 v svld voltage level6 note 5 v svld6 1.39 1.54 1.68 v svld voltage level7 note 5 v svld7 1.25 1.37 1.49 v svld voltage level8 note 5 v svld8 1.11 1.22 1.34 v temperature coefficient +/- 0.2 mv/ c note 4 : level which may not be reached anymore because it can be lower than vddmin. note 5 : this levels can not be reached with the em6521, (software compatibility em6621) 20.6 oscillator conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit temperature stability +15 ... +35 c df/f x dt 0,3 ppm /c input capacitor ref vss cin 5,6 7 8,4 pf output capacitor ref vss cout 12,1 14 15,9 pf transconductance 50mvpp,vddmin gm 2.5 15.0 $9 oscillator start voltage tstart < 10 s ustart vddmin v oscillator start time vdd > vddmin tdosc 0.5 3 s system start time (oscillator + cold start + reset) tdsys 1.5 4 s oscillation detector frequency vdd > vddmin t detfreq 12 khz
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 65 20.7 dc characteristics - i/o pins conditions: t= 0 ... 60c (unless otherwise specified) parameter conditions symb min. typ. max. unit input low voltage ports a,b,sp,test,reset v il vss 0.3vdd v qin v il vss 0.1vreg v qout (note 7) input high voltage ports a,b,sp,test,reset v ih 0.7vdd vdd v qin v ih 0.9vreg vreg v qout (note 7) output low current vdd=3.0v , vol=0.15v i ol 1.8 ma port b,sp, vdd=3.0v , vol=0.30v i ol 3.6 ma strobe, vdd=3.0v , vol=0.50v i ol 5.8 ma buzzer vdd=3.0v , vol=1.00v i ol 7 11.0 ma output high current vdd=3.0v, voh= vdd-0.15v i oh -1.2 ma port b,sp, vdd=3.0v , voh= vdd-0.30v i oh -2.4 ma strobe, vdd=3.0v , voh= vdd-0.50v i oh -3.9 ma buzzer vdd=3.0v , voh= vdd-1.00v i oh -7.0 -4.5 ma input pull-down vdd=3.0v, pin at 3.0v, 25 c r pd 15k ohm test, reset input pull-down vdd=3.0v, pin at 3.0v, 25 c r pd 70k 100k 130k ohm port a,b,sp input pull-up vdd=3.0v, pin at 0.0v, 25 c r pu 72k 103k 134k ohm port a,b,sp note 7 ; qout (osc2) is used only with quartz.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 66 20.8 lcd seg[20:1] outputs conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit driver impedance level 0 iout = 5 m a, ext. supply r segvl0 20 kohm driver impedance level 1 iout = 5 m a, ext supply r segvl1 20 kohm driver impedance level 2 iout = 5 m a, ext supply r segvl2 20 kohm driver impedance level 3 iout = 5 m a, ext supply r segvl3 20 kohm 20.9 lcd com[4:1] outputs conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit driver impedance level 0 iout = 5 m a, ext. supply r comvl0 10 kohm driver impedance level 1 iout = 5 m a, ext. supply r comvl1 10 kohm driver impedance level 2 iout = 5 m a, ext supply r comvl2 10 kohm driver impedance level 3 iout = 5 m a, ext supply rcomvl3 10 kohm 20.10 dc output component conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit dc output component no load v dc_com 20 mv 20.11 lcd voltage multiplier conditions: t=25 c, all multiplier capacitors 100nf, freq=512hz. (unless otherwise specified) parameter conditions symb. min. typ. max. unit voltage bias level 1 1 $ordg v vl1 0.95 1.05 1.17 v voltage bias level 2 1 $ordg v vl2 2.10 v voltage bias level 3 1 $ordg v vl3 3.15 v temp dependency v v l1 1 $ordg?& dv vl1 /dt -4.9 mv/c
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 67 21 die, pad location and size
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 68 22 tqf52 package dimensions the default package for the em6521 microcontroller is the tqpf52 10x10x1 mm. d d1 a e see detail "b" package outline, tqfp, 10x10 mm body, top view b see detail "a" e odd lead sides even lead sides detail "a" all dimensions in millimeters 0.22 min. 0.05 0.45 e n b l a 1 a d d 2 1 a o l y m b 52 0.65 bsc 0.32 0.60 0.38 0.75 10.00 bsc. 12.00 bsc. 1.0 typ. 0.15 1.20 max. tqfp52 s a1 a2 l detail "b" 1.00 ref. 0.20 min. 0.08 r. min. 0-7 0 min. 0.08/0.20 r. 1.00/0.10 mm form, 1.0 mm thick
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 69 23 ordering information the em6521 should be used for engineering purposes only. no volume production must be planned. 23.1 packaged devices em6521 vvv p f vvv : version (version number given by em microelectronic marin sa) p : package type, g = tqfp 52 pin f : delivery form b = eia real (tape) d = trays (plate) this gives below ordering information: em6521 vvv g d 23.2 die form die form for rom version olny. em6521 vvv df th b vvv : version (version number given by em microelectronic marin sa) df : die form , wa = wafer sw = sawn wafer/frame wp = waffle pack st = sticky tape th : thickness, 08 = 8 mils (203um) 11 = 11 mils (280um), standard 15 = 15 mils (380um) 21 = 21 mils (533um) 27 = 27 mils (686um), not backlapped b : bumps, a = without bumps b = with bumps this gives below ordering information: em6521 vvv df th b please contact em headquarters or your local em office for any other detail. also refer to page 60 for additional ordering information.
em6521 for engineering only ? em microelectronic-marin sa, 9/99, rev. b/275 70 em microelectronic-marin sa, ch-2074 marin, switzerland, tel. +41 32 755 51 11, fax. +41 32 755 54 03 updates date ,name version chapter concerned old version (text, figure, etc.) new version (text, figure, etc.) 15.12.98 jag a/247 all - initial version 21.9.99 jag b/275 all - new header: for engineering only 21.9.99 jag b/275 20 temp range C20 to 85c temp range 0 to 60c em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.

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